Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
  • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
  • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
  • H10D84/65—Integrated injection logic
  • H10D84/658—Integrated injection logic integrated in combination with analog structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
  • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive

Landscapes

• Read Only Memory (AREA)
• Semiconductor Memories (AREA)

Applications Claiming Priority (1)

Publications (1)

Family

ID=21896235

Family Applications (1)

Country Status (4)

Families Citing this family (2)

Family Cites Families (5)

• 1980
  • 1980-05-08 DE DE19803017636 patent/DE3017636A1/en not_active Withdrawn
  • 1980-05-09 GB GB8015459A patent/GB2052905B/en not_active Expired
  • 1980-05-09 FR FR8010399A patent/FR2456369A1/en active Pending
  • 1980-05-09 JP JP6079380A patent/JPS5694A/en active Pending

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