JPS569853A - Buffer invalidation system - Google Patents

Buffer invalidation system

Info

Publication number
JPS569853A
JPS569853A JP8401079A JP8401079A JPS569853A JP S569853 A JPS569853 A JP S569853A JP 8401079 A JP8401079 A JP 8401079A JP 8401079 A JP8401079 A JP 8401079A JP S569853 A JPS569853 A JP S569853A
Authority
JP
Japan
Prior art keywords
control part
processing
priority
signal
priority level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8401079A
Other languages
Japanese (ja)
Other versions
JPS6010360B2 (en
Inventor
Hideo Iyota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54084010A priority Critical patent/JPS6010360B2/en
Publication of JPS569853A publication Critical patent/JPS569853A/en
Publication of JPS6010360B2 publication Critical patent/JPS6010360B2/en
Expired legal-status Critical Current

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To lessen an overhead by normally making the priority level of buffer invalidation BI processing lower and then by making it higher in a move-in.
CONSTITUTION: In the system having processors PC with respectively-characteristic buffer storages BS and a main memory unit, each PC is provided with BI storage part 10 stored temporarily with BI information, BI control part 11 and priority-level control part 12 that control a priority level by using BS3-1. When the contents of BS of other PC are rewritten, the BI command is stored in storage part 10 and the data entered in BS3-1 is invalidated by the command through control part 12. The priority level of a BI processing request is normally made lowest. At this time, BI existence signal BIEMP or BI processing signal BIP has been input to OR circuit 13, but once move-in MVIN operation is performed, signal MVIN makes FF15 generate no output through AND circuit 14, so that control part 12 will give the top priority to the BI request processing from control part 11.
COPYRIGHT: (C)1981,JPO&Japio
JP54084010A 1979-07-04 1979-07-04 Buffer invalidation method Expired JPS6010360B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54084010A JPS6010360B2 (en) 1979-07-04 1979-07-04 Buffer invalidation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54084010A JPS6010360B2 (en) 1979-07-04 1979-07-04 Buffer invalidation method

Publications (2)

Publication Number Publication Date
JPS569853A true JPS569853A (en) 1981-01-31
JPS6010360B2 JPS6010360B2 (en) 1985-03-16

Family

ID=13818616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54084010A Expired JPS6010360B2 (en) 1979-07-04 1979-07-04 Buffer invalidation method

Country Status (1)

Country Link
JP (1) JPS6010360B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019928U (en) * 1983-07-19 1985-02-12 株式会社神戸製鋼所 Flow rate measuring device for powder and granular materials in solid-gas two-phase flow

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6019928U (en) * 1983-07-19 1985-02-12 株式会社神戸製鋼所 Flow rate measuring device for powder and granular materials in solid-gas two-phase flow

Also Published As

Publication number Publication date
JPS6010360B2 (en) 1985-03-16

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