JPS5698A - Partial write-in system for memory device - Google Patents

Partial write-in system for memory device

Info

Publication number
JPS5698A
JPS5698A JP7468779A JP7468779A JPS5698A JP S5698 A JPS5698 A JP S5698A JP 7468779 A JP7468779 A JP 7468779A JP 7468779 A JP7468779 A JP 7468779A JP S5698 A JPS5698 A JP S5698A
Authority
JP
Japan
Prior art keywords
bit
circuit
output
given
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7468779A
Other languages
Japanese (ja)
Other versions
JPS6128145B2 (en
Inventor
Shigeru Kaneko
Shiro Hoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7468779A priority Critical patent/JPS5698A/en
Publication of JPS5698A publication Critical patent/JPS5698A/en
Publication of JPS6128145B2 publication Critical patent/JPS6128145B2/ja
Granted legal-status Critical Current

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Abstract

PURPOSE: To enable partial write-in to the memory device with less number of components and a simple circuit, by tentative memory of syndrome less in the bit number.
CONSTITUTION: The 0.1 in the output of the data register 9 are given to 0,1 of the error correction circuit 7 respectively, where one bit error correction is made. The output of the correction circuit 7 is given to the error detection circuit 3 and is the write-in data to the main memory unit MS together with the output of the humming bit generating circuit 4. The humming bit produced at the detection circuit 3 and that read out are collated at the coincidence circuit 5, and one bit error detection output is given to the syndrome register 10 and tentatively stored. The output of the register 10 is given to the error bit decoder 6 and the result of decoding is fed to the correction circuit 7, where one bit error correction is made for the read out data.
COPYRIGHT: (C)1981,JPO&Japio
JP7468779A 1979-06-15 1979-06-15 Partial write-in system for memory device Granted JPS5698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7468779A JPS5698A (en) 1979-06-15 1979-06-15 Partial write-in system for memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7468779A JPS5698A (en) 1979-06-15 1979-06-15 Partial write-in system for memory device

Publications (2)

Publication Number Publication Date
JPS5698A true JPS5698A (en) 1981-01-06
JPS6128145B2 JPS6128145B2 (en) 1986-06-28

Family

ID=13554370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7468779A Granted JPS5698A (en) 1979-06-15 1979-06-15 Partial write-in system for memory device

Country Status (1)

Country Link
JP (1) JPS5698A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0340651U (en) * 1989-03-31 1991-04-18

Also Published As

Publication number Publication date
JPS6128145B2 (en) 1986-06-28

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