JPS57100691A - Memory access control system - Google Patents
Memory access control systemInfo
- Publication number
- JPS57100691A JPS57100691A JP17631080A JP17631080A JPS57100691A JP S57100691 A JPS57100691 A JP S57100691A JP 17631080 A JP17631080 A JP 17631080A JP 17631080 A JP17631080 A JP 17631080A JP S57100691 A JPS57100691 A JP S57100691A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- ram3
- address
- rom1
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
Landscapes
- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE:To modify the contents of an ROM easily by reading the contents of the ROM during reading operation after a power source is put to work, by writing data in an RAM by writing operation, and then by permitting the RAM to be read and written. CONSTITUTION:When a power source is put to work and a readout address, a chip selection signal CS, and a signal R for an ROM1 are supplied, a control RAM3 has a data output 0 and its inverted signal turns on the terminal CS of the ROM1 to read contents which correspond to the input address. Then, the 1st writing operation is performed and when a write address, a signal CS and a signal W are supplied, the signal W is supplied to the RAM3, whose data is boosted to a Vcc, so that a 1 is written in the corresponding address of the RAM3. Further, a control circuit 5 inputs the inverted signal of the data output of the RAM3 to the terminal CS of the ROM1, and write data is written in the corresponding address of the RAM2. Then, reading from and writing to the RAM2 are performed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17631080A JPS57100691A (en) | 1980-12-13 | 1980-12-13 | Memory access control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17631080A JPS57100691A (en) | 1980-12-13 | 1980-12-13 | Memory access control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57100691A true JPS57100691A (en) | 1982-06-22 |
Family
ID=16011345
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17631080A Pending JPS57100691A (en) | 1980-12-13 | 1980-12-13 | Memory access control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57100691A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59177778A (en) * | 1983-03-28 | 1984-10-08 | Chino Works Ltd | Electronic device |
| JPS6050688A (en) * | 1983-08-29 | 1985-03-20 | Shinko Electric Co Ltd | Memory circuit |
| JPH051952U (en) * | 1991-06-19 | 1993-01-14 | 東京電機工業株式會社 | Electric heater device |
-
1980
- 1980-12-13 JP JP17631080A patent/JPS57100691A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59177778A (en) * | 1983-03-28 | 1984-10-08 | Chino Works Ltd | Electronic device |
| JPS6050688A (en) * | 1983-08-29 | 1985-03-20 | Shinko Electric Co Ltd | Memory circuit |
| JPH051952U (en) * | 1991-06-19 | 1993-01-14 | 東京電機工業株式會社 | Electric heater device |
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