JPS57105016A - Clock source switching system - Google Patents
Clock source switching systemInfo
- Publication number
- JPS57105016A JPS57105016A JP18149980A JP18149980A JPS57105016A JP S57105016 A JPS57105016 A JP S57105016A JP 18149980 A JP18149980 A JP 18149980A JP 18149980 A JP18149980 A JP 18149980A JP S57105016 A JPS57105016 A JP S57105016A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- gate
- stage
- delaying circuit
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Exchange Systems With Centralized Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Monitoring And Testing Of Exchanges (AREA)
Abstract
PURPOSE:To guarantee the continuity of a clock when switching a clock source, by detecting a clock (0) level, taking the timing in a delaying circuit, normalizing it, and synchronizing the clock. CONSTITUTION:When a switching signal applied to a clock source selecting signal supply port 105' of ''1'' system is switched at a point 204, signals of supply ports 105, 105' points become waveforms 202, 202', and the first stage of a delaying circuit 109' of ''1'' system is set to ''1''. When the first stage of a delaying circuit 109 of ''0'' system is set to ''0'', gate signals 107, 108 become ''0'' level, a gate of a clock oscillation source 101 is closed, a clock to ''0'' system and ''1'' system is stopped, and a gate signal 106 is made to pass through. Subsequently, when the second stage of the circuit 109' is set to ''1'', the second stage of the delaying circuit 109 of ''0'' system is set to ''0''. Subsequently, when the third stages of the circuits 109, 109' are set to ''0'' and ''1'', respectively, a gate to which gate signals 107', 108' are supplied is opened, and a clock waveform synchronizing with waveforms 203, 203' is fetched once again to supply ports 104, 104' from a new clock oscillation source 101'.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18149980A JPS57105016A (en) | 1980-12-22 | 1980-12-22 | Clock source switching system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18149980A JPS57105016A (en) | 1980-12-22 | 1980-12-22 | Clock source switching system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57105016A true JPS57105016A (en) | 1982-06-30 |
| JPS6250034B2 JPS6250034B2 (en) | 1987-10-22 |
Family
ID=16101822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18149980A Granted JPS57105016A (en) | 1980-12-22 | 1980-12-22 | Clock source switching system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57105016A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5822429A (en) * | 1981-08-04 | 1983-02-09 | Nec Corp | Clock switching circuit |
| JPS59133622A (en) * | 1983-01-21 | 1984-08-01 | Oki Electric Ind Co Ltd | Clock switching control system |
| JPS6010830A (en) * | 1983-06-29 | 1985-01-21 | Fujitsu Ltd | System switching system |
| JPS6095623A (en) * | 1983-10-31 | 1985-05-29 | Hitachi Ltd | Information processing system |
| JPS60502274A (en) * | 1983-11-07 | 1985-12-26 | モトロ−ラ・インコ−ポレ−テツド | Synthetic clock microcomputer saves power |
| JPS62192815A (en) * | 1986-02-20 | 1987-08-24 | Fujitsu Ltd | Clock switching circuit |
| JPH086854A (en) * | 1993-12-23 | 1996-01-12 | Unisys Corp | Outboard-file-cache external processing complex |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3936212A1 (en) * | 1989-10-31 | 1991-05-02 | Gebr Hennig Gmbh | METHOD FOR PRODUCING A TELESCOPE COVER |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5368944A (en) * | 1976-12-01 | 1978-06-19 | Toshiba Corp | Clock conroller |
| JPS55944A (en) * | 1978-06-19 | 1980-01-07 | Fujitsu Ltd | Clock switching system |
-
1980
- 1980-12-22 JP JP18149980A patent/JPS57105016A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5368944A (en) * | 1976-12-01 | 1978-06-19 | Toshiba Corp | Clock conroller |
| JPS55944A (en) * | 1978-06-19 | 1980-01-07 | Fujitsu Ltd | Clock switching system |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5822429A (en) * | 1981-08-04 | 1983-02-09 | Nec Corp | Clock switching circuit |
| JPS59133622A (en) * | 1983-01-21 | 1984-08-01 | Oki Electric Ind Co Ltd | Clock switching control system |
| JPS6010830A (en) * | 1983-06-29 | 1985-01-21 | Fujitsu Ltd | System switching system |
| JPS6095623A (en) * | 1983-10-31 | 1985-05-29 | Hitachi Ltd | Information processing system |
| JPS60502274A (en) * | 1983-11-07 | 1985-12-26 | モトロ−ラ・インコ−ポレ−テツド | Synthetic clock microcomputer saves power |
| JPS62192815A (en) * | 1986-02-20 | 1987-08-24 | Fujitsu Ltd | Clock switching circuit |
| JPH086854A (en) * | 1993-12-23 | 1996-01-12 | Unisys Corp | Outboard-file-cache external processing complex |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6250034B2 (en) | 1987-10-22 |
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