JPS57106934A - Common bus controlling system - Google Patents
Common bus controlling systemInfo
- Publication number
- JPS57106934A JPS57106934A JP18349980A JP18349980A JPS57106934A JP S57106934 A JPS57106934 A JP S57106934A JP 18349980 A JP18349980 A JP 18349980A JP 18349980 A JP18349980 A JP 18349980A JP S57106934 A JPS57106934 A JP S57106934A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- allotment
- request
- sent
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To shorten the allotment switching control time of a common bus by holding the consent discrimination of a bus allotment request by stopping the generation of a time pulse when the bus allotment request is sent from an input and output equipment while a processor uses the common bus. CONSTITUTION:Input and output I/O adapters 7-9 are cascaded. For example, a processor 1 sends a bus allotment request to a direct memory access control part 2 to receive the allotment of a common bus 6, and when a bus allotment request B is sent from the I/Os 7-9 during access to a memory 5, the control part holds the rejection discrimination of the request B to stop the transmission of a master clock F. THen the transmission of the clock F is restarted after the use of the bus 6 by the processor 1 ends, and an allotment consent discrimination signal D for the use of the bus 6 is sent to the I/O having sent the request B. Therefore, even if the I/O having received the allotment of the bus 6 sends the request B during access to the common bus by the processor 1, the request is not rejected immediately, so it is unnecessary to resend the bus allotment request B, thus shortening the bus allotment switching control time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18349980A JPS6024496B2 (en) | 1980-12-24 | 1980-12-24 | Common bus control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18349980A JPS6024496B2 (en) | 1980-12-24 | 1980-12-24 | Common bus control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57106934A true JPS57106934A (en) | 1982-07-03 |
| JPS6024496B2 JPS6024496B2 (en) | 1985-06-13 |
Family
ID=16136887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18349980A Expired JPS6024496B2 (en) | 1980-12-24 | 1980-12-24 | Common bus control method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6024496B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02151398A (en) * | 1988-12-03 | 1990-06-11 | Hori Takeshi | Powder forming method |
-
1980
- 1980-12-24 JP JP18349980A patent/JPS6024496B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6024496B2 (en) | 1985-06-13 |
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