JPS57106935A - Setting system for channel logical address - Google Patents

Setting system for channel logical address

Info

Publication number
JPS57106935A
JPS57106935A JP18355380A JP18355380A JPS57106935A JP S57106935 A JPS57106935 A JP S57106935A JP 18355380 A JP18355380 A JP 18355380A JP 18355380 A JP18355380 A JP 18355380A JP S57106935 A JPS57106935 A JP S57106935A
Authority
JP
Japan
Prior art keywords
channel
addresses
logical addresses
logical address
chp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18355380A
Other languages
Japanese (ja)
Other versions
JPS5943773B2 (en
Inventor
Rei Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18355380A priority Critical patent/JPS5943773B2/en
Publication of JPS57106935A publication Critical patent/JPS57106935A/en
Publication of JPS5943773B2 publication Critical patent/JPS5943773B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To set two kinds of logical address for a 4-channel processor, by giving the channel controller two logical addresses for a noncross call and a cross call mode, and by switching them automatically. CONSTITUTION:When the OS of a system O is operated by a system 1, logical addresses 2 and 3 of a channel processor CHP at a noncross call mode and logical addresses 0 and 1 at a cross call mode are prepared. When the CHP logical addresses 2 and 3 are set in a floating channel address register FCA, the addresses 2 and 3 are given to channel processors 3-2 and 3-3, and when the CHP logical addresses 0 and 1 are set in the FCA, the channel processors 3-2 and 3-3 are given the addresses 0 and 1. Thus, the OS of one system is operated by the other system.
JP18355380A 1980-12-24 1980-12-24 Channel logical address setting method Expired JPS5943773B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18355380A JPS5943773B2 (en) 1980-12-24 1980-12-24 Channel logical address setting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18355380A JPS5943773B2 (en) 1980-12-24 1980-12-24 Channel logical address setting method

Publications (2)

Publication Number Publication Date
JPS57106935A true JPS57106935A (en) 1982-07-03
JPS5943773B2 JPS5943773B2 (en) 1984-10-24

Family

ID=16137812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18355380A Expired JPS5943773B2 (en) 1980-12-24 1980-12-24 Channel logical address setting method

Country Status (1)

Country Link
JP (1) JPS5943773B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008126547A (en) * 2006-11-21 2008-06-05 National Univ Corp Shizuoka Univ Wooden structure material that can utilize low-density wood, connection structure using the same, structure using the connection structure, and method for forming the connection structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008126547A (en) * 2006-11-21 2008-06-05 National Univ Corp Shizuoka Univ Wooden structure material that can utilize low-density wood, connection structure using the same, structure using the connection structure, and method for forming the connection structure

Also Published As

Publication number Publication date
JPS5943773B2 (en) 1984-10-24

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