JPS5710879A - Picture memory device - Google Patents
Picture memory deviceInfo
- Publication number
- JPS5710879A JPS5710879A JP8480680A JP8480680A JPS5710879A JP S5710879 A JPS5710879 A JP S5710879A JP 8480680 A JP8480680 A JP 8480680A JP 8480680 A JP8480680 A JP 8480680A JP S5710879 A JPS5710879 A JP S5710879A
- Authority
- JP
- Japan
- Prior art keywords
- picture
- order
- element data
- write
- storage area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/0007—Image acquisition
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Television Signal Processing For Recording (AREA)
- Image Input (AREA)
Abstract
PURPOSE:To omit a refreshing circuit of a memory control device, by shifting in order a picture element data at regular intervals and executing a write control, in a picture memory device for storing a picture which is similar to a static picture. CONSTITUTION:An image to be photographed, which is similar to a static picture is photographed by a television camera 1, is A/D-converted 2, and a picture element data is stored in order in a picture memory 3' which has used a dynamic RAM. In order to store a picture element data which is A/D converted in order, a picture memory area is divided into plural area 3A, 3B, 3C, 3D, and each storage area is designated by common address information. A picture element data is also divided into each field, and is written in order and periodically to each corresponding storage area 3A, 3B, 3C, 3D by each field unit. As for a read-out control, immediately after the write-in, a data of an address corresponding to a write-in address of each storage area is read out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8480680A JPS5710879A (en) | 1980-06-20 | 1980-06-20 | Picture memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8480680A JPS5710879A (en) | 1980-06-20 | 1980-06-20 | Picture memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5710879A true JPS5710879A (en) | 1982-01-20 |
Family
ID=13840951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8480680A Pending JPS5710879A (en) | 1980-06-20 | 1980-06-20 | Picture memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5710879A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010890A (en) * | 1983-06-29 | 1985-01-21 | Fujitsu Ltd | Picture display system |
| US8064282B2 (en) | 2007-10-30 | 2011-11-22 | Kawasaki Microelectronics Inc. | Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same |
| US8194090B2 (en) | 2008-01-18 | 2012-06-05 | Kawasaki Microelectronics, Inc. | Method of controlling frame memory, memory control circuit, and image processing apparatus including the memory control circuit |
-
1980
- 1980-06-20 JP JP8480680A patent/JPS5710879A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010890A (en) * | 1983-06-29 | 1985-01-21 | Fujitsu Ltd | Picture display system |
| US8064282B2 (en) | 2007-10-30 | 2011-11-22 | Kawasaki Microelectronics Inc. | Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same |
| US8194090B2 (en) | 2008-01-18 | 2012-06-05 | Kawasaki Microelectronics, Inc. | Method of controlling frame memory, memory control circuit, and image processing apparatus including the memory control circuit |
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