JPS57124955A - Phase locked loop circuit - Google Patents

Phase locked loop circuit

Info

Publication number
JPS57124955A
JPS57124955A JP56010337A JP1033781A JPS57124955A JP S57124955 A JPS57124955 A JP S57124955A JP 56010337 A JP56010337 A JP 56010337A JP 1033781 A JP1033781 A JP 1033781A JP S57124955 A JPS57124955 A JP S57124955A
Authority
JP
Japan
Prior art keywords
signals
phase
signal
output
logical sum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56010337A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6331140B2 (2
Inventor
Takao Kizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Nihon Musen KK
Original Assignee
Japan Radio Co Ltd
Nihon Musen KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd, Nihon Musen KK filed Critical Japan Radio Co Ltd
Priority to JP56010337A priority Critical patent/JPS57124955A/ja
Publication of JPS57124955A publication Critical patent/JPS57124955A/ja
Publication of JPS6331140B2 publication Critical patent/JPS6331140B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2271—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals
    • H04L27/2273—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses only the demodulated signals associated with quadrature demodulation, e.g. Costas loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
JP56010337A 1981-01-27 1981-01-27 Phase locked loop circuit Granted JPS57124955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56010337A JPS57124955A (en) 1981-01-27 1981-01-27 Phase locked loop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56010337A JPS57124955A (en) 1981-01-27 1981-01-27 Phase locked loop circuit

Publications (2)

Publication Number Publication Date
JPS57124955A true JPS57124955A (en) 1982-08-04
JPS6331140B2 JPS6331140B2 (2) 1988-06-22

Family

ID=11747374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56010337A Granted JPS57124955A (en) 1981-01-27 1981-01-27 Phase locked loop circuit

Country Status (1)

Country Link
JP (1) JPS57124955A (2)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238119A (ja) * 2008-03-28 2009-10-15 Giga-Byte Technology Co Ltd メインボード用電力管理方法及びシステム

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009238119A (ja) * 2008-03-28 2009-10-15 Giga-Byte Technology Co Ltd メインボード用電力管理方法及びシステム

Also Published As

Publication number Publication date
JPS6331140B2 (2) 1988-06-22

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