JPS5712497A - Integrated circuit device for memory - Google Patents
Integrated circuit device for memoryInfo
- Publication number
- JPS5712497A JPS5712497A JP8536280A JP8536280A JPS5712497A JP S5712497 A JPS5712497 A JP S5712497A JP 8536280 A JP8536280 A JP 8536280A JP 8536280 A JP8536280 A JP 8536280A JP S5712497 A JPS5712497 A JP S5712497A
- Authority
- JP
- Japan
- Prior art keywords
- data
- read
- circuit
- write
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 241001640034 Heteropterys Species 0.000 abstract 1
- 210000004027 cell Anatomy 0.000 abstract 1
- 210000000352 storage cell Anatomy 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE:To realize a high-speed test at a time and every data group, by providing a test data generating circuit and a means to write and read the data group into an IC for memory and then comparing the read-out data withe an expected value with every data group. CONSTITUTION:When a read/write control signal 104 is in a write state, a test data 403 is given and written to storage cells j0-jn (i=0,1-n) from a test data generating circuit 7 via a write data selection circuit 4 and in the form of write data 210-21n. While in case the signal 104 is in a reading state, a reading is carried out at a time to cells j0-jn. At the same time, the data 403 is delivered from the circuit 7 to be supplied to a comparator 6. The circuit 6 compares data 200-20n with an expected value data 403. If a coincidence is obtained, a coincidence signal 405 is applied to a read data selection circuit 5. Then the signal 405 is delivered from the circuit 5 by a read data control signal 401 and in the form of a read data 101.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55085362A JPS6031039B2 (en) | 1980-06-24 | 1980-06-24 | Integrated circuit device for memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55085362A JPS6031039B2 (en) | 1980-06-24 | 1980-06-24 | Integrated circuit device for memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5712497A true JPS5712497A (en) | 1982-01-22 |
| JPS6031039B2 JPS6031039B2 (en) | 1985-07-19 |
Family
ID=13856595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55085362A Expired JPS6031039B2 (en) | 1980-06-24 | 1980-06-24 | Integrated circuit device for memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6031039B2 (en) |
-
1980
- 1980-06-24 JP JP55085362A patent/JPS6031039B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6031039B2 (en) | 1985-07-19 |
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