JPS57127251A - Extra-high-speed computer system having data prefetching mechanism - Google Patents

Extra-high-speed computer system having data prefetching mechanism

Info

Publication number
JPS57127251A
JPS57127251A JP1181381A JP1181381A JPS57127251A JP S57127251 A JPS57127251 A JP S57127251A JP 1181381 A JP1181381 A JP 1181381A JP 1181381 A JP1181381 A JP 1181381A JP S57127251 A JPS57127251 A JP S57127251A
Authority
JP
Japan
Prior art keywords
latch
subblocks
designated
control signal
extra
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1181381A
Other languages
Japanese (ja)
Inventor
Yoshiharu Shigei
Koreo Nakamura
Makoto Hasegawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP1181381A priority Critical patent/JPS57127251A/en
Publication of JPS57127251A publication Critical patent/JPS57127251A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To realize a high-speed operation, by providing a parallel processing means which generates several kinds of data of the next instruction during the instruction execution. CONSTITUTION:An operation device group 2 consists esentially of subblocks 20, 40, and 60, and sublocks consist of adders 21, 41, and 61, subtractors 22, 42, and 62, mutipliers 23, 43, and 63, and dividers 24, 44, and 64 respectively. Latch circuit groups 10, 30, and 50 are installed in the input side of subblocks 20, 40, and 60 respectively. Every latch cirlcuit constituting latch circuit groups latches data on an input data bus 3 in accordance with a control signal on a control signal line 5 outputted from a system control device 1. All operation devices in each subblock are operated simultaneously except operation devices whose operation is not designated. Similarly, latch circuits are operated simultaneously except latch circuits whose operation is not designated.
JP1181381A 1981-01-29 1981-01-29 Extra-high-speed computer system having data prefetching mechanism Pending JPS57127251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1181381A JPS57127251A (en) 1981-01-29 1981-01-29 Extra-high-speed computer system having data prefetching mechanism

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1181381A JPS57127251A (en) 1981-01-29 1981-01-29 Extra-high-speed computer system having data prefetching mechanism

Publications (1)

Publication Number Publication Date
JPS57127251A true JPS57127251A (en) 1982-08-07

Family

ID=11788244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1181381A Pending JPS57127251A (en) 1981-01-29 1981-01-29 Extra-high-speed computer system having data prefetching mechanism

Country Status (1)

Country Link
JP (1) JPS57127251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6113379A (en) * 1984-06-28 1986-01-21 Fujitsu Ltd Image processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50153840A (en) * 1974-05-31 1975-12-11

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50153840A (en) * 1974-05-31 1975-12-11

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6113379A (en) * 1984-06-28 1986-01-21 Fujitsu Ltd Image processor

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