JPS57155653A - Controller of central processor - Google Patents

Controller of central processor

Info

Publication number
JPS57155653A
JPS57155653A JP4061181A JP4061181A JPS57155653A JP S57155653 A JPS57155653 A JP S57155653A JP 4061181 A JP4061181 A JP 4061181A JP 4061181 A JP4061181 A JP 4061181A JP S57155653 A JPS57155653 A JP S57155653A
Authority
JP
Japan
Prior art keywords
signal
mono
circuit
supplied
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4061181A
Other languages
Japanese (ja)
Inventor
Akira Matsushita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4061181A priority Critical patent/JPS57155653A/en
Publication of JPS57155653A publication Critical patent/JPS57155653A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To prevent the malfunction of a CPU, by detecting a change of the cycle of a reference signal if said change occurs and inhibiting the writing of data into a memory.
CONSTITUTION: A video signal Sv superposed by a digital signal Sd given from a terminal 26 is supplied to a waveform circuit 27 and a timing address generating circuit 29. A pulse (b) synchronizing with the synchronizing signal V of the signal Sv is delivered through an output terminal 29C of the circuit 29 and supplied to a mono-multi 30. The mono-multi 30 produces a signal C of a prescribed width (r), and the signal C holds an H level to be supplied to a mono- multi 31 although the synchronism of the signal Sv varies. The mono-multi 31 delivers a signal (d) of width (t) and opens a gate 32. A signal (e) coincident with the synchronizing period of the signal Sd is delivered through an output terminal 29A of the circuit 29. The operation of a CPU21 is discontinued with a signal (f) that is transmitted only when the signal (d) is applied to the gate 32. At the same time, gates 28 and 33 are controlled to lead the signal Sd and the address signal given from an output terminal 29B to an RAM23. As a result, the writing carried out to the RAM by a signal V' obtained by varying the cycle of the signal V can be prevented.
COPYRIGHT: (C)1982,JPO&Japio
JP4061181A 1981-03-20 1981-03-20 Controller of central processor Pending JPS57155653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4061181A JPS57155653A (en) 1981-03-20 1981-03-20 Controller of central processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4061181A JPS57155653A (en) 1981-03-20 1981-03-20 Controller of central processor

Publications (1)

Publication Number Publication Date
JPS57155653A true JPS57155653A (en) 1982-09-25

Family

ID=12585317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4061181A Pending JPS57155653A (en) 1981-03-20 1981-03-20 Controller of central processor

Country Status (1)

Country Link
JP (1) JPS57155653A (en)

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