JPS57192069A - Insulated gate field effect semiconductor device - Google Patents

Insulated gate field effect semiconductor device

Info

Publication number
JPS57192069A
JPS57192069A JP56076580A JP7658081A JPS57192069A JP S57192069 A JPS57192069 A JP S57192069A JP 56076580 A JP56076580 A JP 56076580A JP 7658081 A JP7658081 A JP 7658081A JP S57192069 A JPS57192069 A JP S57192069A
Authority
JP
Japan
Prior art keywords
region
type
semiconductor device
field effect
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56076580A
Other languages
Japanese (ja)
Inventor
Akira Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56076580A priority Critical patent/JPS57192069A/en
Publication of JPS57192069A publication Critical patent/JPS57192069A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices

Landscapes

  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To contrive to reduce the occupying area of element and to reduce the size of an insulated gate field effect semiconductor device by a method wherein the source or drain region of the second MISFET is connected directly to the source or drain region of the first MISFET with the reverse conductive region. CONSTITUTION:The N<+> type semiconductor region 3, 4 and an N<+> type Si gate electrode 6 are provided in the region surrounded with SiO2 films 2 on the surface of a P type Si substrate 1, and an N channel MOSFET Q3 or Q4 is provided. A polycrystalline Si layer 7 for formation of the P channel MOSFET Q1 or Q2 is provided from the upper part of the film 2 being at the neighborhood of the MOSFET up to the position coming in contact directly with the drain region 3 of the FET Q3 or Q4. The P<+> type source region 8 and drain region 9 are provided in the layer 7 thereof. The reverse conductive type (N<+> type) region 12 is provided in the layer 7 in the condition coming in contact with the region 9, andf moreover connected directly to the region 3. A P-N junction diode D1 or D2 is formed by existence of the region 12 thereof between the region 9, and the regions 9, 3 are connected directly through the diode D1 or D2.
JP56076580A 1981-05-22 1981-05-22 Insulated gate field effect semiconductor device Pending JPS57192069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56076580A JPS57192069A (en) 1981-05-22 1981-05-22 Insulated gate field effect semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56076580A JPS57192069A (en) 1981-05-22 1981-05-22 Insulated gate field effect semiconductor device

Publications (1)

Publication Number Publication Date
JPS57192069A true JPS57192069A (en) 1982-11-26

Family

ID=13609204

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56076580A Pending JPS57192069A (en) 1981-05-22 1981-05-22 Insulated gate field effect semiconductor device

Country Status (1)

Country Link
JP (1) JPS57192069A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59217292A (en) * 1983-05-23 1984-12-07 Nec Corp Semiconductor memory cell
JPH01214156A (en) * 1988-02-23 1989-08-28 Nec Corp bipolar storage
US5521401A (en) * 1992-08-21 1996-05-28 Sgs-Thomson Microelectronics, Inc. P-N junction in a vertical memory cell that creates a high resistance load
US5821136A (en) * 1989-01-18 1998-10-13 Stmicroelectronics, Inc. Inverted field-effect device with polycrystalline silicon/germanium channel
US6140684A (en) * 1997-06-24 2000-10-31 Stmicroelectronic, Inc. SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5562771A (en) * 1978-11-02 1980-05-12 Toshiba Corp Integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5562771A (en) * 1978-11-02 1980-05-12 Toshiba Corp Integrated circuit device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59217292A (en) * 1983-05-23 1984-12-07 Nec Corp Semiconductor memory cell
JPH01214156A (en) * 1988-02-23 1989-08-28 Nec Corp bipolar storage
US5821136A (en) * 1989-01-18 1998-10-13 Stmicroelectronics, Inc. Inverted field-effect device with polycrystalline silicon/germanium channel
US5521401A (en) * 1992-08-21 1996-05-28 Sgs-Thomson Microelectronics, Inc. P-N junction in a vertical memory cell that creates a high resistance load
US6140684A (en) * 1997-06-24 2000-10-31 Stmicroelectronic, Inc. SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers

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