JPS57196647A - Clock signal reproducer - Google Patents

Abstract

PURPOSE:To achieve stability against temperature and noise, by using a delay circuit and a double balance type differential circuit, obtaining a clock reproducing pulse and determining the pulse width with an amount of delay of the delay circuit. CONSTITUTION:An input signal is applied to a differential circuit 102 directly and also via a delay circuit 101. This circuit 101 has a delay time corresponding to about a half the clock signal period to be reproduced and this delayed output and the input signal are two inputs to the double balance type differential circuit 102. The output of the circuit 102 is inputted to a tuning circuit 103 having the same tuning frequency as the clock frequency to be reproduced and the tuning output is outputted with a zero level comparator 104 as a pulse signal. Since the clock reproducing pulse is obtained by using the delay circuit and the double balance type differential circuit, the pulse width can be determined with an amount of delay of the delay circuit, the operation is stable against temperature change and noise and the phase of the reproduced clock can be made stable.