JPS5720020A - Receiver - Google Patents
ReceiverInfo
- Publication number
- JPS5720020A JPS5720020A JP9450180A JP9450180A JPS5720020A JP S5720020 A JPS5720020 A JP S5720020A JP 9450180 A JP9450180 A JP 9450180A JP 9450180 A JP9450180 A JP 9450180A JP S5720020 A JPS5720020 A JP S5720020A
- Authority
- JP
- Japan
- Prior art keywords
- output
- switch
- closed
- down counter
- 100khz
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J7/00—Automatic frequency control; Automatic scanning over a band of frequencies
- H03J7/18—Automatic scanning over a band of frequencies
- H03J7/20—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element
- H03J7/28—Automatic scanning over a band of frequencies where the scanning is accomplished by varying the electrical characteristics of a non-mechanically adjustable element using counters or frequency dividers
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
PURPOSE:To speed receiving operation by making a sweep speed higher fast feeding than in step feeding. CONSTITUTION:When an up switch 2 is closed within 500ms, a switch 4 is also closed and an FF10 is set, so that an output Q is at a lever H for 500ms from this point in time. Consequently, an output pulse is applied from a reference oscillator 1 to the up the up input of an up-down counter via an AND gate 11 to increase the frequency in steps of 100kHz. Then, the output is supplied to a PLL circuit 9, so the reception frequency is swept by only 100kHz. When the switch 2 is pushed continuously for >=500ms, the FF10 is inverted 500ms later, so AND gates 10 and 11 are closed while AND gates 13 and 14 are opened. Consequently, the output of an oscillator 1 is applied to the up-down counter 7 via the gate 13, so that the up- down counter 7 goes up in steps of 300kHz from the reception frequency, set by step feeding, as a preset value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9450180A JPS5720020A (en) | 1980-07-09 | 1980-07-09 | Receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9450180A JPS5720020A (en) | 1980-07-09 | 1980-07-09 | Receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5720020A true JPS5720020A (en) | 1982-02-02 |
Family
ID=14112052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9450180A Pending JPS5720020A (en) | 1980-07-09 | 1980-07-09 | Receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5720020A (en) |
-
1980
- 1980-07-09 JP JP9450180A patent/JPS5720020A/en active Pending
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