JPS57201934A - Memory switching system of buffer circuit - Google Patents

Memory switching system of buffer circuit

Info

Publication number
JPS57201934A
JPS57201934A JP8566581A JP8566581A JPS57201934A JP S57201934 A JPS57201934 A JP S57201934A JP 8566581 A JP8566581 A JP 8566581A JP 8566581 A JP8566581 A JP 8566581A JP S57201934 A JPS57201934 A JP S57201934A
Authority
JP
Japan
Prior art keywords
memory
transmission line
address
speed
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8566581A
Other languages
Japanese (ja)
Other versions
JPS639708B2 (en
Inventor
Masao Iida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP8566581A priority Critical patent/JPS57201934A/en
Publication of JPS57201934A publication Critical patent/JPS57201934A/en
Publication of JPS639708B2 publication Critical patent/JPS639708B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bidirectional Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE: To compose a speed converting circuit of a normal memory and a minimum number of counters, by switching and using the memory constituting a buffer circuit for speed conversion when a signal processing speed is different from the signal transmission speed of a transmission line.
CONSTITUTION: With respect to reception from a transmission line, a received signal from the transmission line 40 is waveform-shaped by a line iterface circuit 30, and then written in the high-order digit half address of a memory 70 at prescribed time in the period of a transmission line signal block by the address assignment of a counter 61. Then, the contents of the high-order digit address of the memory 70 are read at a speed specified by a counter 62 and sent to a terminal equipment 10. At this time, the received signal from the transmission line is written in the high-order digit half address of the other memory 71 by the address assignment of the counter 61 and in a next period, the contents of the high-order digit address of the memory 71 are read through the counter 62 and sent to the terminal equipments 10. Similarly, those two memories 70 and 71 are switched and used, thus performing speed conversion.
COPYRIGHT: (C)1982,JPO&Japio
JP8566581A 1981-06-05 1981-06-05 Memory switching system of buffer circuit Granted JPS57201934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8566581A JPS57201934A (en) 1981-06-05 1981-06-05 Memory switching system of buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8566581A JPS57201934A (en) 1981-06-05 1981-06-05 Memory switching system of buffer circuit

Publications (2)

Publication Number Publication Date
JPS57201934A true JPS57201934A (en) 1982-12-10
JPS639708B2 JPS639708B2 (en) 1988-03-01

Family

ID=13865112

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8566581A Granted JPS57201934A (en) 1981-06-05 1981-06-05 Memory switching system of buffer circuit

Country Status (1)

Country Link
JP (1) JPS57201934A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134687A (en) * 1983-12-23 1985-07-17 Mitsubishi Corp video conference telephone equipment
JPS61278238A (en) * 1985-06-04 1986-12-09 Hitachi Ltd Address deciding circuit for transmitter terminal equipment
JPS63169133A (en) * 1987-01-05 1988-07-13 Oki Electric Ind Co Ltd Single core two-way time division optical transmission equipment
JPS63240149A (en) * 1987-03-27 1988-10-05 Yokogawa Electric Corp Data transmission buffer circuit
JPH06224943A (en) * 1993-01-22 1994-08-12 Kokusai Electric Co Ltd Buffer and its data conversion method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60134687A (en) * 1983-12-23 1985-07-17 Mitsubishi Corp video conference telephone equipment
JPS61278238A (en) * 1985-06-04 1986-12-09 Hitachi Ltd Address deciding circuit for transmitter terminal equipment
JPS63169133A (en) * 1987-01-05 1988-07-13 Oki Electric Ind Co Ltd Single core two-way time division optical transmission equipment
JPS63240149A (en) * 1987-03-27 1988-10-05 Yokogawa Electric Corp Data transmission buffer circuit
JPH06224943A (en) * 1993-01-22 1994-08-12 Kokusai Electric Co Ltd Buffer and its data conversion method

Also Published As

Publication number Publication date
JPS639708B2 (en) 1988-03-01

Similar Documents

Publication Publication Date Title
JPS5737925A (en) High-speed hadamard converter
EP0093527A3 (en) Sequential data block address processing circuits
JPS5248425A (en) Receiving system of facsimile signal
JPS56122567A (en) Digital talking equipment
JPS5415620A (en) Buffer memory unit
JPS5518775A (en) Data transfer system
JPS5759242A (en) Buffer memory circuit of computer output equipment
JPS56149627A (en) Fault informing system among plural devices
JPS55157182A (en) Buffer memory
JPS5488742A (en) Data buffer managing and processing system in communication control processor
JPS54103611A (en) Time sharing message channel system
JPS55118170A (en) Memory access device
JPS5534742A (en) Memory control system
JPS5354435A (en) Information transfer system
JPS52128001A (en) Automatic address adding system
JPS55142476A (en) Address conversion system for information processing system
JPS5570172A (en) Two-dimensional sequential coding system
JPS5294721A (en) Information processing system using tv communication system
JPS55139682A (en) Buffer memory control system
JPS5544657A (en) Decentralized control system
JPS5436141A (en) Information transfer system
JPS57162023A (en) Communication control system
JPS55118290A (en) Connection system for representative of extension
JPS52149924A (en) Address converter
JPS5617424A (en) Data transfer system