JPS57201936A - Integrated logical circuit - Google Patents

Integrated logical circuit

Info

Publication number
JPS57201936A
JPS57201936A JP56085593A JP8559381A JPS57201936A JP S57201936 A JPS57201936 A JP S57201936A JP 56085593 A JP56085593 A JP 56085593A JP 8559381 A JP8559381 A JP 8559381A JP S57201936 A JPS57201936 A JP S57201936A
Authority
JP
Japan
Prior art keywords
flip
flop circuits
circuit
cascaded
constitute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56085593A
Other languages
Japanese (ja)
Inventor
Yasunori Ouchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56085593A priority Critical patent/JPS57201936A/en
Publication of JPS57201936A publication Critical patent/JPS57201936A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To constitute diverse testing paths by providing a means for providing the feedback of the output of a circuit composed of cascaded flip-flop circuits to the input, and a means for placing the flip-flop circuits in a data through state. CONSTITUTION:Flip-flop circuits 11 in an integrated logical circuit are connected to and disconnected from a combinational circuit 10 by a flip-flop input control gate group 12, and disconnected flip-flop circuits 11 are cascaded through the gate group 12 to constitute a shift register. When a shift signal 4 is ''0'', the flip- flop circuits 11 are connected to the combinational circuit 10 and when the shift signal 4 is ''1'', the flip-flop circuits are cascaded to constitute the shift register. Further, a feedback means consists of a ring signal 8, an inverting circuit 12e, an AND gate 12c, etc.
JP56085593A 1981-06-05 1981-06-05 Integrated logical circuit Pending JPS57201936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56085593A JPS57201936A (en) 1981-06-05 1981-06-05 Integrated logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56085593A JPS57201936A (en) 1981-06-05 1981-06-05 Integrated logical circuit

Publications (1)

Publication Number Publication Date
JPS57201936A true JPS57201936A (en) 1982-12-10

Family

ID=13863113

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56085593A Pending JPS57201936A (en) 1981-06-05 1981-06-05 Integrated logical circuit

Country Status (1)

Country Link
JP (1) JPS57201936A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119443A (en) * 1982-12-27 1984-07-10 Toshiba Corp Logic circuit
JPS61144800A (en) * 1984-12-18 1986-07-02 Fujitsu Ltd Semiconductor integrated circuit having built-in memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119443A (en) * 1982-12-27 1984-07-10 Toshiba Corp Logic circuit
JPS61144800A (en) * 1984-12-18 1986-07-02 Fujitsu Ltd Semiconductor integrated circuit having built-in memory

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