JPS57202157A - Packet exchanger - Google Patents
Packet exchangerInfo
- Publication number
- JPS57202157A JPS57202157A JP8737981A JP8737981A JPS57202157A JP S57202157 A JPS57202157 A JP S57202157A JP 8737981 A JP8737981 A JP 8737981A JP 8737981 A JP8737981 A JP 8737981A JP S57202157 A JPS57202157 A JP S57202157A
- Authority
- JP
- Japan
- Prior art keywords
- section
- controlling
- circuit
- function
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
PURPOSE:To increase the processing ability of a central processing system with a low cost constitution, by including a function which has been performed with the software from the central processing system in a line control section. CONSTITUTION:A packet exchanger 1A consists of a main storage section 5, a central processing section 6, line control sections 7-1-7-n corresponding to lines l1-ln, and a bus control circuit 15 controlling the competition of a service processor 14 and a bus. The line control sections 7-1-7-n consist of an HDLC procedure processing circuit 8 which performs a function assembling a bit serial data from the lines l1-ln, a function decomposing characters into a bit serial data, and a high level data link control (HDLC) procedure processing circuit 8 which performs HDLC procedure processing, a microprocessor 9 controlling the operation of each section of the line controlling sections 7-1-7-n with a program incorporated in a packet processing ROM10, buffuer memory 11 and a DMA circuit 17.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8737981A JPS57202157A (en) | 1981-06-05 | 1981-06-05 | Packet exchanger |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8737981A JPS57202157A (en) | 1981-06-05 | 1981-06-05 | Packet exchanger |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS57202157A true JPS57202157A (en) | 1982-12-10 |
Family
ID=13913256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8737981A Pending JPS57202157A (en) | 1981-06-05 | 1981-06-05 | Packet exchanger |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57202157A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4861004A (en) * | 1971-12-01 | 1973-08-27 | ||
| JPS5571339A (en) * | 1978-11-22 | 1980-05-29 | Fujitsu Ltd | Packet transfer circuit system |
-
1981
- 1981-06-05 JP JP8737981A patent/JPS57202157A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4861004A (en) * | 1971-12-01 | 1973-08-27 | ||
| JPS5571339A (en) * | 1978-11-22 | 1980-05-29 | Fujitsu Ltd | Packet transfer circuit system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS5634198A (en) | Releaving method of deficient bit of semiconductor memory | |
| JPS57127207A (en) | Numerical controlling system | |
| JPS57202157A (en) | Packet exchanger | |
| JPS55162130A (en) | Program control system of terminal equipment | |
| JPS55105760A (en) | Memory control unit | |
| JPS53139939A (en) | Memory addressing method | |
| JPS56111905A (en) | Programmable sequence controller | |
| JPS54157447A (en) | Automatic control unit | |
| JPS556671A (en) | Data processing system | |
| JPS5394849A (en) | Control unit for interruption process | |
| JPS5585941A (en) | Dma system for data transmission and reception unit | |
| JPS57157698A (en) | System switching control method for electronic switching system | |
| JPS5424553A (en) | Control system for data transfer | |
| JPS5429534A (en) | Adding system of optional functions to composite terminal | |
| JPS5640347A (en) | Data transmission system | |
| JPS52129345A (en) | Computation control system | |
| JPS5640346A (en) | Data transmission system | |
| JPS5697124A (en) | Connection disconnection system for terminal device | |
| JPS556668A (en) | Interruption processing system of data transfer system | |
| JPS5544657A (en) | Decentralized control system | |
| JPS52130244A (en) | Memory unit providing error control function | |
| JPS5380144A (en) | Data transmission control system | |
| JPS55119729A (en) | Data processor | |
| JPS55105734A (en) | Communication control system | |
| JPS533033A (en) | Code branching system for intelligent terminal unit |