JPS57211892A - Analog interface circuit - Google Patents

Analog interface circuit

Info

Publication number
JPS57211892A
JPS57211892A JP56096036A JP9603681A JPS57211892A JP S57211892 A JPS57211892 A JP S57211892A JP 56096036 A JP56096036 A JP 56096036A JP 9603681 A JP9603681 A JP 9603681A JP S57211892 A JPS57211892 A JP S57211892A
Authority
JP
Japan
Prior art keywords
time slot
transmitting
receiving
sent
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56096036A
Other languages
Japanese (ja)
Inventor
Takuji Mukaemachi
Takeji Aizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56096036A priority Critical patent/JPS57211892A/en
Publication of JPS57211892A publication Critical patent/JPS57211892A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Interface Circuits In Exchanges (AREA)

Abstract

PURPOSE:To simplify the configuration of a switchboard by providing the switchboard with transmitting and receiving buffer memories and connecting a pulse feeding circuit for generating time slot pulses corresponding to the specified time slot numbers assigned to the encoder and decoder sides and the transmitting and receiving highway sides of said buffer memories. CONSTITUTION:A controlling device 3 selects idle time slots on transmitting and receiving highways 5, 6 individually in response to a calling request of a telephone set 1 and outputs the selected time slot numbers to memories 25a, 25b through a control circuit 20 to store the numbers in the memories. A coincidence circuit 26a generates a strobe signal when a counter 27 counting clocks CLK indicates the time position corresponding to the time slot stored in the memory 25A. Consequently a voice from the telephone set 1 is sent to an encoder 23 and shift registers 28a, 28b successively. When the coincidence circuit 26b generates a strobe pulse at the time of the time slot of the memory 25b, a signal is sent from the register 28b to the transmitting highway 5. The signal on the receiving highway 6 is sent to the telephone set 1 through registers 29b, 29a and an decoder 24 reversely against said direction.
JP56096036A 1981-06-23 1981-06-23 Analog interface circuit Pending JPS57211892A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56096036A JPS57211892A (en) 1981-06-23 1981-06-23 Analog interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56096036A JPS57211892A (en) 1981-06-23 1981-06-23 Analog interface circuit

Publications (1)

Publication Number Publication Date
JPS57211892A true JPS57211892A (en) 1982-12-25

Family

ID=14154235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56096036A Pending JPS57211892A (en) 1981-06-23 1981-06-23 Analog interface circuit

Country Status (1)

Country Link
JP (1) JPS57211892A (en)

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