JPS5724082A - Computer system - Google Patents

Computer system

Info

Publication number
JPS5724082A
JPS5724082A JP9733780A JP9733780A JPS5724082A JP S5724082 A JPS5724082 A JP S5724082A JP 9733780 A JP9733780 A JP 9733780A JP 9733780 A JP9733780 A JP 9733780A JP S5724082 A JPS5724082 A JP S5724082A
Authority
JP
Japan
Prior art keywords
coincidence
logic
discriminator
space
tlb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9733780A
Other languages
Japanese (ja)
Other versions
JPS5953634B2 (en
Inventor
Tsutomu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55097337A priority Critical patent/JPS5953634B2/en
Publication of JPS5724082A publication Critical patent/JPS5724082A/en
Publication of JPS5953634B2 publication Critical patent/JPS5953634B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To ensure a forcible coincidence for the space discriminator and display the common space, by providing a common segment bit in the entry of an address conversion index buffer mechanism in a system which is available to both a virtual computer and a normal computer. CONSTITUTION:When a retrieval is given to an address conversion index buffer mechanism TLB1, the contents of an entry corresponding to an address part AM is read to a reading register 11. In case both common segment bits CS0 and CS1 which are given from a bit producing circuit 5 are logic 0, a coincidence between space discriminators ID-0 and ID-1 is turned to the TLB-FOUND condition. Then the discriminator ID-0 is forcibly defined to be coincident when the bits CS0 and CS1 are logic 1 and 0 respectively, and a coincidence of the discriminator ID-1 is identical with the TLB-FOUND condition. Furthermore a coincidence is forcibly secured between the ID-0 and ID-1 in case both CS0 and CS1 are logic 1.
JP55097337A 1980-07-15 1980-07-15 computer system Expired JPS5953634B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55097337A JPS5953634B2 (en) 1980-07-15 1980-07-15 computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55097337A JPS5953634B2 (en) 1980-07-15 1980-07-15 computer system

Publications (2)

Publication Number Publication Date
JPS5724082A true JPS5724082A (en) 1982-02-08
JPS5953634B2 JPS5953634B2 (en) 1984-12-26

Family

ID=14189664

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55097337A Expired JPS5953634B2 (en) 1980-07-15 1980-07-15 computer system

Country Status (1)

Country Link
JP (1) JPS5953634B2 (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119110U (en) * 1983-01-28 1984-08-11 ヤンマー農機株式会社 transplant machine
JPS60142451A (en) * 1983-12-29 1985-07-27 Fujitsu Ltd Address conversion control system
JPS61108116U (en) * 1984-12-20 1986-07-09
JPS6336704A (en) * 1986-07-30 1988-02-17 安久津　義人 Automatic ridge matching method of cultivator
JPS63126406A (en) * 1986-11-17 1988-05-30 日農機製工株式会社 Automatic levee width matching method of transplanter of beet
JPH01255945A (en) * 1988-04-06 1989-10-12 Hitachi Ltd Address converter in virtual computer
JP2009151650A (en) * 2007-12-21 2009-07-09 Hitachi Ltd Computer virtualization apparatus, program thereof, and method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59119110U (en) * 1983-01-28 1984-08-11 ヤンマー農機株式会社 transplant machine
JPS60142451A (en) * 1983-12-29 1985-07-27 Fujitsu Ltd Address conversion control system
JPS61108116U (en) * 1984-12-20 1986-07-09
JPS6336704A (en) * 1986-07-30 1988-02-17 安久津　義人 Automatic ridge matching method of cultivator
JPS63126406A (en) * 1986-11-17 1988-05-30 日農機製工株式会社 Automatic levee width matching method of transplanter of beet
JPH01255945A (en) * 1988-04-06 1989-10-12 Hitachi Ltd Address converter in virtual computer
JP2009151650A (en) * 2007-12-21 2009-07-09 Hitachi Ltd Computer virtualization apparatus, program thereof, and method thereof

Also Published As

Publication number Publication date
JPS5953634B2 (en) 1984-12-26

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