JPS573059A - Detecting method for defective packaging of element of logical circuit - Google Patents

Detecting method for defective packaging of element of logical circuit

Info

Publication number
JPS573059A
JPS573059A JP7710480A JP7710480A JPS573059A JP S573059 A JPS573059 A JP S573059A JP 7710480 A JP7710480 A JP 7710480A JP 7710480 A JP7710480 A JP 7710480A JP S573059 A JPS573059 A JP S573059A
Authority
JP
Japan
Prior art keywords
impedance
logical circuit
earth
pin
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7710480A
Other languages
Japanese (ja)
Inventor
Toshiro Kosaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7710480A priority Critical patent/JPS573059A/en
Publication of JPS573059A publication Critical patent/JPS573059A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To detect both mis-position and unpackaging of IC packaging by comparing the impedance between the earth pin and other pin of the IC packaged to a printed circuit board with the impedance when it is normally packaged. CONSTITUTION:With the earth side of a logical circuit element such as the one shown in the figure kept at 0V, input pin IN1, IN2 terminal points are forced by constant current and the impedance of the IN1, IN2 terminal points to the earth is measured. Since this results in the smaller impedance of the IN1, IN2 terminals and the large impedance of the Vcc terminal point, the detection of the mis-position, type change, etc. of the integrated circuits is made possible. The impedance of the IN1, IN2 terminal is a low impedance but if there is a defective element, it rises to a high impedance and this makes the detection possible.
JP7710480A 1980-06-10 1980-06-10 Detecting method for defective packaging of element of logical circuit Pending JPS573059A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7710480A JPS573059A (en) 1980-06-10 1980-06-10 Detecting method for defective packaging of element of logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7710480A JPS573059A (en) 1980-06-10 1980-06-10 Detecting method for defective packaging of element of logical circuit

Publications (1)

Publication Number Publication Date
JPS573059A true JPS573059A (en) 1982-01-08

Family

ID=13624469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7710480A Pending JPS573059A (en) 1980-06-10 1980-06-10 Detecting method for defective packaging of element of logical circuit

Country Status (1)

Country Link
JP (1) JPS573059A (en)

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