JPS573155A - Input and output control circuit for memory device - Google Patents

Input and output control circuit for memory device

Info

Publication number
JPS573155A
JPS573155A JP7495980A JP7495980A JPS573155A JP S573155 A JPS573155 A JP S573155A JP 7495980 A JP7495980 A JP 7495980A JP 7495980 A JP7495980 A JP 7495980A JP S573155 A JPS573155 A JP S573155A
Authority
JP
Japan
Prior art keywords
and1
ffn
outputs
memory
andn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7495980A
Other languages
Japanese (ja)
Inventor
Yoshio Maniwa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP7495980A priority Critical patent/JPS573155A/en
Publication of JPS573155A publication Critical patent/JPS573155A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To make efficient use of the processing capability of a memory at its maximum, by not providing priority levels for respective input/output ports and by making it possible that memory use requests use all ports when these memory use requests are generated simultaneously. CONSTITUTION:When use request signals REQ1-REQn are generated, corresponding latch circuits L1-Ln are set. Their outputs set corresponding FF1-FFn to queue for use permission. Set FF1-FFn trigger a one shot monostable multivibrator OSM in accordance with timings of scanning due to a clock signal CLOCK1' to open AND circuits AND1-ANDn, AND1' and AND2'. Consequently, address request signals AVA1-AVAn are outputted from AND1-ANDn by Q outputs of set FF1-FFn, and a write or read signal is outputted from one of AND1' and AND2'. L1-Ln are reset at the fall time of Q' outputs.
JP7495980A 1980-06-05 1980-06-05 Input and output control circuit for memory device Pending JPS573155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7495980A JPS573155A (en) 1980-06-05 1980-06-05 Input and output control circuit for memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7495980A JPS573155A (en) 1980-06-05 1980-06-05 Input and output control circuit for memory device

Publications (1)

Publication Number Publication Date
JPS573155A true JPS573155A (en) 1982-01-08

Family

ID=13562355

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7495980A Pending JPS573155A (en) 1980-06-05 1980-06-05 Input and output control circuit for memory device

Country Status (1)

Country Link
JP (1) JPS573155A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02220293A (en) * 1988-12-19 1990-09-03 Bull Hn Inf Syst Inc Double-port reading/ writing memory
WO2007018043A1 (en) * 2005-08-05 2007-02-15 Rohm Co., Ltd. Ram control device and memory device using the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5074948A (en) * 1973-11-02 1975-06-19
JPS52149038A (en) * 1976-06-07 1977-12-10 Hitachi Ltd Interface system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5074948A (en) * 1973-11-02 1975-06-19
JPS52149038A (en) * 1976-06-07 1977-12-10 Hitachi Ltd Interface system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02220293A (en) * 1988-12-19 1990-09-03 Bull Hn Inf Syst Inc Double-port reading/ writing memory
WO2007018043A1 (en) * 2005-08-05 2007-02-15 Rohm Co., Ltd. Ram control device and memory device using the same
US7843762B2 (en) 2005-08-05 2010-11-30 Rohm Co., Ltd. RAM control device and memory device using the same
JP5000514B2 (en) * 2005-08-05 2012-08-15 ローム株式会社 RAM controller and memory device using the same

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