JPS573299A - Memory integrated circuit - Google Patents
Memory integrated circuitInfo
- Publication number
- JPS573299A JPS573299A JP7644280A JP7644280A JPS573299A JP S573299 A JPS573299 A JP S573299A JP 7644280 A JP7644280 A JP 7644280A JP 7644280 A JP7644280 A JP 7644280A JP S573299 A JPS573299 A JP S573299A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- cell array
- memory cell
- circuits
- written
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Static Random-Access Memory (AREA)
Abstract
PURPOSE:To obtain a memory integrated circuit which can be tested by adding a simple circuit, by comparing a test pattern, outputted from an address arithmetic circuit, with a readout outpt obtain by passing the said pattern through a memory. CONSTITUTION:Written data WD is passed through an input and output circuit 3 and then written in an address position in a memory cell array 1 specified by row and column selecting circuits 2 and 4, and it is also read out and outputted from the circuit 3. On the application of a test signal TE, a data selecting circuit 5 selects a test pattern signal WD, generated by an address arithmetic circuit 6, according to all or some of addresses. Then, this signal WD and data written in the memory cell array 1 via the circuits 3 and read out from the memory cell array 1 are compared mutually by a comparing circuit 7, thereby testing the memory cell array 1 by adding simple circuits 6 and 7, etc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7644280A JPS573299A (en) | 1980-06-06 | 1980-06-06 | Memory integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7644280A JPS573299A (en) | 1980-06-06 | 1980-06-06 | Memory integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS573299A true JPS573299A (en) | 1982-01-08 |
Family
ID=13605261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7644280A Pending JPS573299A (en) | 1980-06-06 | 1980-06-06 | Memory integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS573299A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61145799A (en) * | 1984-12-20 | 1986-07-03 | Fujitsu Ltd | Semiconductor integrated circuit incorporating memory |
| JPS61296600A (en) * | 1985-06-24 | 1986-12-27 | Nec Ic Microcomput Syst Ltd | Storage device |
| JPS6366799A (en) * | 1986-09-08 | 1988-03-25 | Toshiba Corp | Semiconductor memory device |
| JPS63102098A (en) * | 1986-10-02 | 1988-05-06 | アメリカン テレフォン アンド テレグラフ カムパニー | Integrated circuit |
-
1980
- 1980-06-06 JP JP7644280A patent/JPS573299A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61145799A (en) * | 1984-12-20 | 1986-07-03 | Fujitsu Ltd | Semiconductor integrated circuit incorporating memory |
| JPS61296600A (en) * | 1985-06-24 | 1986-12-27 | Nec Ic Microcomput Syst Ltd | Storage device |
| JPS6366799A (en) * | 1986-09-08 | 1988-03-25 | Toshiba Corp | Semiconductor memory device |
| JPS63102098A (en) * | 1986-10-02 | 1988-05-06 | アメリカン テレフォン アンド テレグラフ カムパニー | Integrated circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE3174062D1 (en) | Testing embedded arrays in large scale integrated circuits | |
| KR870010551A (en) | Dynamic RAM | |
| KR910005321A (en) | Semiconductor memory | |
| KR920013472A (en) | Semiconductor memory | |
| KR870009384A (en) | Semiconductor memory | |
| JPS57189397A (en) | Semiconductor storage device | |
| JPS573299A (en) | Memory integrated circuit | |
| KR970017693A (en) | Test circuit | |
| JPS643748A (en) | Test device for software logical device | |
| JPS5542391A (en) | Method and device for testing shift rfgister | |
| KR950006876A (en) | Roll call circuit | |
| DE69505806D1 (en) | METHOD AND DEVICE FOR TESTING A MEMORY WITH A PARALLEL BLOCK-WRITE OPERATION | |
| KR900005474A (en) | Improved inspection circuit | |
| JPS5564699A (en) | Semiconductor integrated-circuit memory | |
| JPS55135731A (en) | Particle analyzer | |
| JPS5794995A (en) | Memory test system | |
| JPS5472924A (en) | Semiconductor memory inspection equipment | |
| JPS6432500A (en) | Semiconductor storage device | |
| JPS5798197A (en) | Multiplexing memory device | |
| JPS57169860A (en) | Address testing equipment | |
| SU1010651A1 (en) | Memory device having self-testing capability | |
| SU739650A1 (en) | Dynamic memory on semiconductor devices | |
| JPS55141679A (en) | Ic tester | |
| JPS57111474A (en) | Test system for memory printed board | |
| JPS5670476A (en) | Measuring method for address hold time and address setup time of randam access memory |