JPS5733478A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5733478A
JPS5733478A JP10562380A JP10562380A JPS5733478A JP S5733478 A JPS5733478 A JP S5733478A JP 10562380 A JP10562380 A JP 10562380A JP 10562380 A JP10562380 A JP 10562380A JP S5733478 A JPS5733478 A JP S5733478A
Authority
JP
Japan
Prior art keywords
address
data
buffer
real
converting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10562380A
Other languages
Japanese (ja)
Inventor
Yuzo Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10562380A priority Critical patent/JPS5733478A/en
Publication of JPS5733478A publication Critical patent/JPS5733478A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To ensure a high-speed reading of a data out of a data buffer, by giving the indexing to an address converting buffer simultaneously with the growing of a logic address. CONSTITUTION:The output data of a base address switching circuit 405 is used as a set address 454 of both the 1st and 2nd address converting buffers 412 and 413. Either the 1st real address 462 or the 2nd real address 463 which are taken out of the buffers 412 and 413 is selected through a real address siwtching circuit 414 and set to a real address register 417. A selection signal 464 is produced by an address control circuit 415, and at the same time the success or failure of indexing is examined for the address converting buffer. Then both a data buffer directory and a data buffer 411 are indexed by the register 417 to obtain the data 465.
JP10562380A 1980-07-31 1980-07-31 Information processor Pending JPS5733478A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10562380A JPS5733478A (en) 1980-07-31 1980-07-31 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10562380A JPS5733478A (en) 1980-07-31 1980-07-31 Information processor

Publications (1)

Publication Number Publication Date
JPS5733478A true JPS5733478A (en) 1982-02-23

Family

ID=14412609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10562380A Pending JPS5733478A (en) 1980-07-31 1980-07-31 Information processor

Country Status (1)

Country Link
JP (1) JPS5733478A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07191911A (en) * 1993-12-27 1995-07-28 Nec Corp Address converter and microprocessor computation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07191911A (en) * 1993-12-27 1995-07-28 Nec Corp Address converter and microprocessor computation method

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