JPS5735342A - Manufacturing method of large scale integrated circuit - Google Patents

Manufacturing method of large scale integrated circuit

Info

Publication number
JPS5735342A
JPS5735342A JP11020380A JP11020380A JPS5735342A JP S5735342 A JPS5735342 A JP S5735342A JP 11020380 A JP11020380 A JP 11020380A JP 11020380 A JP11020380 A JP 11020380A JP S5735342 A JPS5735342 A JP S5735342A
Authority
JP
Japan
Prior art keywords
cell
inferior
cells
good quality
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11020380A
Other languages
Japanese (ja)
Inventor
Ryuichi Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11020380A priority Critical patent/JPS5735342A/en
Publication of JPS5735342A publication Critical patent/JPS5735342A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To perform efficiently the connection of functional blocks of good quality only, by a method wherein characteristics of a number of the functional blocks are inspected from mutual wiring through connection wiring and if an inferior functional block is found its connection wiring will be eliminated. CONSTITUTION:A number of functional block cells A, B, bus-lines Sx, Sy, outside connection parts 4-7 and a power source line P are composed on a semiconductor wafer 1. Each cell and the bus-lines are connected with chip selection lines Cx, Cy and the electric characteristics of each cell is inspected with signal current through the outside connection parts. If one cell is found to be inferior, the chip selection lines of the inferior cell will be eliminated by means of a lazer beam or the like and only cells of good quality are selectively connected. Thus it is unnecessary to provide probing pads on each cell, so that the chip size is reduced and the cells of good quality can be connected with high efficiency.
JP11020380A 1980-08-13 1980-08-13 Manufacturing method of large scale integrated circuit Pending JPS5735342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11020380A JPS5735342A (en) 1980-08-13 1980-08-13 Manufacturing method of large scale integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11020380A JPS5735342A (en) 1980-08-13 1980-08-13 Manufacturing method of large scale integrated circuit

Publications (1)

Publication Number Publication Date
JPS5735342A true JPS5735342A (en) 1982-02-25

Family

ID=14529660

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11020380A Pending JPS5735342A (en) 1980-08-13 1980-08-13 Manufacturing method of large scale integrated circuit

Country Status (1)

Country Link
JP (1) JPS5735342A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58153672A (en) * 1982-03-10 1983-09-12 Nippon Telegr & Teleph Corp <Ntt> Recording head with built-in thin film transistor circuit
JPS5989928U (en) * 1982-12-08 1984-06-18 三ツ星ベルト株式会社 Roof waterproof structure with flame retardant properties
JPS621247A (en) * 1985-02-14 1987-01-07 Nec Corp Manufacture of semiconductor device
JPH0376263A (en) * 1989-08-18 1991-04-02 Fujitsu Ltd Wafer scale integrated circuit device
JPH03104758U (en) * 1990-02-14 1991-10-30
JPH04228760A (en) * 1991-04-18 1992-08-18 Tsugio Abe Method 0f constructing water-proof layer in structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492871A (en) * 1972-04-22 1974-01-11
JPS492796A (en) * 1972-03-15 1974-01-11
JPS495677A (en) * 1972-05-04 1974-01-18
JPS4926270A (en) * 1972-07-04 1974-03-08
JPS4933231A (en) * 1972-07-27 1974-03-27
JPS506294A (en) * 1972-07-28 1975-01-22

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS492796A (en) * 1972-03-15 1974-01-11
JPS492871A (en) * 1972-04-22 1974-01-11
JPS495677A (en) * 1972-05-04 1974-01-18
JPS4926270A (en) * 1972-07-04 1974-03-08
JPS4933231A (en) * 1972-07-27 1974-03-27
JPS506294A (en) * 1972-07-28 1975-01-22

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58153672A (en) * 1982-03-10 1983-09-12 Nippon Telegr & Teleph Corp <Ntt> Recording head with built-in thin film transistor circuit
JPS5989928U (en) * 1982-12-08 1984-06-18 三ツ星ベルト株式会社 Roof waterproof structure with flame retardant properties
JPS621247A (en) * 1985-02-14 1987-01-07 Nec Corp Manufacture of semiconductor device
JPH0376263A (en) * 1989-08-18 1991-04-02 Fujitsu Ltd Wafer scale integrated circuit device
JPH03104758U (en) * 1990-02-14 1991-10-30
JPH04228760A (en) * 1991-04-18 1992-08-18 Tsugio Abe Method 0f constructing water-proof layer in structure

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