JPS5739552A - Dividing method for semiconductor chip - Google Patents

Dividing method for semiconductor chip

Info

Publication number
JPS5739552A
JPS5739552A JP55115176A JP11517680A JPS5739552A JP S5739552 A JPS5739552 A JP S5739552A JP 55115176 A JP55115176 A JP 55115176A JP 11517680 A JP11517680 A JP 11517680A JP S5739552 A JPS5739552 A JP S5739552A
Authority
JP
Japan
Prior art keywords
wafer
chips
simplify
cost
reduce
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55115176A
Other languages
Japanese (ja)
Inventor
Tadao Takano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Rectifier Corp Japan Ltd
Original Assignee
International Rectifier Corp Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Rectifier Corp Japan Ltd filed Critical International Rectifier Corp Japan Ltd
Priority to JP55115176A priority Critical patent/JPS5739552A/en
Publication of JPS5739552A publication Critical patent/JPS5739552A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices

Landscapes

  • Dicing (AREA)

Abstract

PURPOSE:To simplify the assembling of a semiconductor chip and to reduce the cost of the chip by bonding a plurality of conductive spacers on one wafer and then dividing it into individual semiconductor chips. CONSTITUTION:A plurality of planar type semiconductor elements in which p-n junctions are disposed on one main surface of one semiconductor wafer sheet are formed, an insulating film 3 of SiO2, glass or the like is then formed, windows are opened at the corresponding positions, and metallized layers 4, 5 are formed to form electrode metals on both surfaces. Subsequently, conductive spacers 16 are connected via a high melting point solder cream 30 to the electrode metal. Thereafter, a wafer is cleaned, is blown, and is then divided into individual semiconductor chips 15. In this manner, it can simplify the assembling steps and can reduce the cost of the chips.
JP55115176A 1980-08-21 1980-08-21 Dividing method for semiconductor chip Pending JPS5739552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55115176A JPS5739552A (en) 1980-08-21 1980-08-21 Dividing method for semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55115176A JPS5739552A (en) 1980-08-21 1980-08-21 Dividing method for semiconductor chip

Publications (1)

Publication Number Publication Date
JPS5739552A true JPS5739552A (en) 1982-03-04

Family

ID=14656221

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55115176A Pending JPS5739552A (en) 1980-08-21 1980-08-21 Dividing method for semiconductor chip

Country Status (1)

Country Link
JP (1) JPS5739552A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5328369U (en) * 1976-08-18 1978-03-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5328369U (en) * 1976-08-18 1978-03-10

Similar Documents

Publication Publication Date Title
US3716907A (en) Method of fabrication of semiconductor device package
JPS56140646A (en) Method of manufacturing semiconductor circuit on semiconductor silicon substrate
GB1043942A (en) Method for connecting semiconductor devices
WO1995027313A1 (en) Method of manufacturing an antifuse with silicon spacers and resulting antifuse
GB1237099A (en) Method of making electrical contact to one or more semiconductor components
GB1200426A (en) Method for providing a planar transistor with heat-dissipating top base and emitter contacts
IE822564L (en) Fabrication a semiconductor device having a phosphosilicate glass layer
EP0039160A3 (en) Methods for bonding conductive bumps to electronic circuitry
EP0152794A3 (en) Multi-layered electrical interconnection structure
JPS56148857A (en) Semiconductor device
JPS57115850A (en) Chip carrier for semiconductor ic
JPS61111582A (en) Process of grounding planar device and ic and product obtained
JPS5745262A (en) Sealing and fitting structure of semiconductor device
JPS5330283A (en) Production of substrates for semiconductor integrated circuits
JPS574147A (en) Semiconductor device and its manufacturing process
JPS57114242A (en) Semiconductor device
JPS55148449A (en) Semiconductor device
JPS57166052A (en) Semiconductor device
JPS5662342A (en) Semiconductor device
JPS56167350A (en) Manufacture of integrated circuit
JPS5771171A (en) Semiconductor device
JPS6421965A (en) Mos transistor
JPS57121239A (en) Semiconductor device
JPS57109350A (en) Semiconductor device
JPS577948A (en) Semiconductor device and its manufacture