JPS574127A - Formation of conductor pattern - Google Patents
Formation of conductor patternInfo
- Publication number
- JPS574127A JPS574127A JP7854780A JP7854780A JPS574127A JP S574127 A JPS574127 A JP S574127A JP 7854780 A JP7854780 A JP 7854780A JP 7854780 A JP7854780 A JP 7854780A JP S574127 A JPS574127 A JP S574127A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- thick
- negative type
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
Landscapes
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Abstract
PURPOSE:To easily form a thick pattern by a method wherein, when a thick conductor pattern such as a metal bump to be used for face-down bonding is formed on an IC substrate, a positive type layer and a negative type layer are laminated and a pattering is performed on the substrate and a resist layer is removed after a conductor layer has been coated on the whole surface. CONSTITUTION:The resist layer 2 of a double laminated layer constitution, consisting of the positive type layer 2a and the thick negative type layer 2b, is formed on the surface of the IC substrate 1 and, after an exposure is performed using a photomask, the above is treated with a negative type developing solution and the photo- sensitive section alone of the layer 2b is remained. Then, under this condition, the substrate 1 is soaked in an alkaline aqueous solution for several minutes, the exposed section of the layer 2a is removed by dissolution, a conductive material such as an In and the like is evaporated on the whole surface, and a conductive layer 3a is formed on the layer 2b and a conductive layer 3b is formed on the exposed substrate 1 respectively, bringing them under a discontinuous condition. Then, the layers 2a and 2b are removed together with the layer 3b located above these layers 2a and 2b, and the thick layer 3b alone is left on the substrate 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7854780A JPS574127A (en) | 1980-06-10 | 1980-06-10 | Formation of conductor pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7854780A JPS574127A (en) | 1980-06-10 | 1980-06-10 | Formation of conductor pattern |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS574127A true JPS574127A (en) | 1982-01-09 |
Family
ID=13664936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7854780A Pending JPS574127A (en) | 1980-06-10 | 1980-06-10 | Formation of conductor pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS574127A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197730A (en) * | 1982-05-12 | 1983-11-17 | Pioneer Electronic Corp | Wiring pattern formation for integrated circuit device |
| JPS6074629A (en) * | 1983-09-30 | 1985-04-26 | Seiko Instr & Electronics Ltd | Formation of thin film pattern |
| JPS6459918A (en) * | 1987-08-31 | 1989-03-07 | Nec Corp | Lift-off flattening process |
| JPH0631556U (en) * | 1992-09-30 | 1994-04-26 | 博彦 小林 | Chair with speaker |
| US6188127B1 (en) | 1995-02-24 | 2001-02-13 | Nec Corporation | Semiconductor packing stack module and method of producing the same |
| US7300864B2 (en) | 2003-10-22 | 2007-11-27 | Samsung Electronics Co., Ltd. | Method for forming solder bump structure |
| CN104465337A (en) * | 2014-12-03 | 2015-03-25 | 复旦大学 | Method for manufacturing metal nanometer slit through PMMA/NEB double-layer glue |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5186972A (en) * | 1975-01-29 | 1976-07-30 | Mitsubishi Electric Corp | HANDOTAISOCHINOSEIZOHOHO |
| JPS5335475A (en) * | 1976-09-14 | 1978-04-01 | Matsushita Electric Ind Co Ltd | Production of semiconductor unit |
-
1980
- 1980-06-10 JP JP7854780A patent/JPS574127A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5186972A (en) * | 1975-01-29 | 1976-07-30 | Mitsubishi Electric Corp | HANDOTAISOCHINOSEIZOHOHO |
| JPS5335475A (en) * | 1976-09-14 | 1978-04-01 | Matsushita Electric Ind Co Ltd | Production of semiconductor unit |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58197730A (en) * | 1982-05-12 | 1983-11-17 | Pioneer Electronic Corp | Wiring pattern formation for integrated circuit device |
| JPS6074629A (en) * | 1983-09-30 | 1985-04-26 | Seiko Instr & Electronics Ltd | Formation of thin film pattern |
| JPS6459918A (en) * | 1987-08-31 | 1989-03-07 | Nec Corp | Lift-off flattening process |
| JPH0631556U (en) * | 1992-09-30 | 1994-04-26 | 博彦 小林 | Chair with speaker |
| US6188127B1 (en) | 1995-02-24 | 2001-02-13 | Nec Corporation | Semiconductor packing stack module and method of producing the same |
| US7300864B2 (en) | 2003-10-22 | 2007-11-27 | Samsung Electronics Co., Ltd. | Method for forming solder bump structure |
| CN104465337A (en) * | 2014-12-03 | 2015-03-25 | 复旦大学 | Method for manufacturing metal nanometer slit through PMMA/NEB double-layer glue |
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