JPS574152A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS574152A
JPS574152A JP7818880A JP7818880A JPS574152A JP S574152 A JPS574152 A JP S574152A JP 7818880 A JP7818880 A JP 7818880A JP 7818880 A JP7818880 A JP 7818880A JP S574152 A JPS574152 A JP S574152A
Authority
JP
Japan
Prior art keywords
grounding wire
circuits
circuit
signal
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7818880A
Other languages
English (en)
Other versions
JPS5840344B2 (ja
Inventor
Hideaki Ito
Takahiko Yamauchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55078188A priority Critical patent/JPS5840344B2/ja
Priority to EP81302502A priority patent/EP0041844B1/en
Priority to DE8181302502T priority patent/DE3175780D1/de
Priority to IE1262/81A priority patent/IE52453B1/en
Priority to US06/272,367 priority patent/US4439841A/en
Publication of JPS574152A publication Critical patent/JPS574152A/ja
Publication of JPS5840344B2 publication Critical patent/JPS5840344B2/ja
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
JP55078188A 1980-06-10 1980-06-10 半導体記憶装置 Expired JPS5840344B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP55078188A JPS5840344B2 (ja) 1980-06-10 1980-06-10 半導体記憶装置
EP81302502A EP0041844B1 (en) 1980-06-10 1981-06-05 Semiconductor integrated circuit devices
DE8181302502T DE3175780D1 (en) 1980-06-10 1981-06-05 Semiconductor integrated circuit devices
IE1262/81A IE52453B1 (en) 1980-06-10 1981-06-08 Semiconductor integrated circuit devices
US06/272,367 US4439841A (en) 1980-06-10 1981-06-10 Semiconductor memory devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55078188A JPS5840344B2 (ja) 1980-06-10 1980-06-10 半導体記憶装置

Publications (2)

Publication Number Publication Date
JPS574152A true JPS574152A (en) 1982-01-09
JPS5840344B2 JPS5840344B2 (ja) 1983-09-05

Family

ID=13654998

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55078188A Expired JPS5840344B2 (ja) 1980-06-10 1980-06-10 半導体記憶装置

Country Status (5)

Country Link
US (1) US4439841A (ja)
EP (1) EP0041844B1 (ja)
JP (1) JPS5840344B2 (ja)
DE (1) DE3175780D1 (ja)
IE (1) IE52453B1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136948A (ja) * 1983-01-18 1984-08-06 エイ・ティ・アンド・ティ・コーポレーション 集積回路チツプ
JPH03133174A (ja) * 1989-10-19 1991-06-06 Toshiba Corp 半導体記憶装置

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0079127A1 (en) * 1981-11-06 1983-05-18 Texas Instruments Incorporated Programmable system component
KR910008099B1 (ko) * 1988-07-21 1991-10-07 삼성반도체통신주식회사 메모리 칩의 파워 및 시그널라인 버싱방법
EP0493615B1 (en) * 1990-07-23 1998-05-20 Seiko Epson Corporation Semiconductor integrated circuit device
JP2894635B2 (ja) * 1990-11-30 1999-05-24 株式会社東芝 半導体記憶装置
GB2268332A (en) * 1992-06-25 1994-01-05 Gen Electric Power transistor with reduced gate resistance and inductance
JP2876963B2 (ja) * 1993-12-15 1999-03-31 日本電気株式会社 半導体装置
EP0747930B1 (en) * 1995-05-19 2000-09-27 STMicroelectronics S.r.l. Electronic device with multiple bonding wires, method of fabrication and method of testing bonding wire integrity
US7422930B2 (en) * 2004-03-02 2008-09-09 Infineon Technologies Ag Integrated circuit with re-route layer and stacked die assembly

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3760384A (en) * 1970-10-27 1973-09-18 Cogar Corp Fet memory chip including fet devices therefor and fabrication method
US4122540A (en) * 1974-03-18 1978-10-24 Signetics Corporation Massive monolithic integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59136948A (ja) * 1983-01-18 1984-08-06 エイ・ティ・アンド・ティ・コーポレーション 集積回路チツプ
JPH03133174A (ja) * 1989-10-19 1991-06-06 Toshiba Corp 半導体記憶装置

Also Published As

Publication number Publication date
IE52453B1 (en) 1987-11-11
US4439841A (en) 1984-03-27
IE811262L (en) 1981-12-10
DE3175780D1 (en) 1987-02-05
EP0041844A3 (en) 1983-06-15
EP0041844A2 (en) 1981-12-16
JPS5840344B2 (ja) 1983-09-05
EP0041844B1 (en) 1986-12-30

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