JPS5745263A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS5745263A
JPS5745263A JP56102356A JP10235681A JPS5745263A JP S5745263 A JPS5745263 A JP S5745263A JP 56102356 A JP56102356 A JP 56102356A JP 10235681 A JP10235681 A JP 10235681A JP S5745263 A JPS5745263 A JP S5745263A
Authority
JP
Japan
Prior art keywords
base
leads
package
metallization
brazed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56102356A
Other languages
Japanese (ja)
Inventor
Esu Fuii Uiriamu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of JPS5745263A publication Critical patent/JPS5745263A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor package 10 has a braze pad region 22 formed near its periphery and a metallization pattern 18 formed on the base 12 for connecting the leads 24 of the lead frame 20 (which is brazed to the base 12) to the semiconductor die 16 which is mounted on the base by bonding means 28. The package 10 has a pressed ceramic base, and the metallization 18 is screen-printed onto the base so that criteria for automatic wire bonding are met. To aid frame alignment an interconnecting member 26 may be employed that is removed from between the leads 24 of frame 20 after the leads 24 have been brazed to the ceramic base 12. A ceramic base having screen-printed metallization thereon may form a leadless chip carrier. <IMAGE>
JP56102356A 1980-07-02 1981-07-02 Package for semiconductor device Pending JPS5745263A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16545780A 1980-07-02 1980-07-02

Publications (1)

Publication Number Publication Date
JPS5745263A true JPS5745263A (en) 1982-03-15

Family

ID=22598970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56102356A Pending JPS5745263A (en) 1980-07-02 1981-07-02 Package for semiconductor device

Country Status (6)

Country Link
JP (1) JPS5745263A (en)
DE (1) DE3123844A1 (en)
FR (1) FR2486307A1 (en)
GB (1) GB2079534A (en)
IT (1) IT8167917A0 (en)
NL (1) NL8102871A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263455A (en) * 1985-09-13 1987-03-20 Hitachi Cable Ltd Manufacture of lead frame
JPS6422043U (en) * 1987-07-30 1989-02-03

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3380082D1 (en) * 1982-10-21 1989-07-20 Abbott Lab A method of establishing electrical connections at a semiconductor device
US4547795A (en) * 1983-03-24 1985-10-15 Bourns, Inc. Leadless chip carrier with frangible shorting bars
WO1989008324A1 (en) * 1988-02-29 1989-09-08 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
US4987475A (en) * 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
FR2750798B1 (en) * 1996-07-02 1998-11-06 Sgs Thomson Microelectronics LOW COST BOX FOR INTEGRATED CIRCUITS MADE IN SMALL QUANTITY

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1288983A (en) * 1968-11-06 1972-09-13
US3550766A (en) * 1969-03-03 1970-12-29 David Nixen Flat electronic package assembly
GB1258870A (en) * 1969-09-29 1971-12-30
US3760090A (en) * 1971-08-19 1973-09-18 Globe Union Inc Electronic circuit package and method for making same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263455A (en) * 1985-09-13 1987-03-20 Hitachi Cable Ltd Manufacture of lead frame
JPS6422043U (en) * 1987-07-30 1989-02-03

Also Published As

Publication number Publication date
NL8102871A (en) 1982-02-01
IT8167917A0 (en) 1981-07-01
FR2486307A1 (en) 1982-01-08
DE3123844A1 (en) 1982-04-08
GB2079534A (en) 1982-01-20

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