JPS5745751A - Time division full duplex communication system - Google Patents

Time division full duplex communication system

Info

Publication number
JPS5745751A
JPS5745751A JP12070780A JP12070780A JPS5745751A JP S5745751 A JPS5745751 A JP S5745751A JP 12070780 A JP12070780 A JP 12070780A JP 12070780 A JP12070780 A JP 12070780A JP S5745751 A JPS5745751 A JP S5745751A
Authority
JP
Japan
Prior art keywords
pulse
circuit
transmission
reception
full duplex
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12070780A
Other languages
Japanese (ja)
Inventor
Harukiyo Kano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12070780A priority Critical patent/JPS5745751A/en
Publication of JPS5745751A publication Critical patent/JPS5745751A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex
    • H04L5/16—Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To speed up and make efficient the full duplex communication system, by making full duplex communication digitally and in time division, through the use of only one line of two-line type among data signal transmission and reception devices. CONSTITUTION:A zero return double current type pulse is transmitted to the secondary winding of a transformer 3A to two-wire lines 5 corresponding to a transmission data signal SDA with a prescribed period. This signal is received at a pulse reception circuit 2B through the primary winding from the secondary winding of a transformer 3B. Since a non-window pulse inversion WPB is given to this circuit 2B, the zero return double current pulse only incoming during ''1'' is detected, and a reception clock pulse RCB and a reception data RDB are demodulated and outputted. The pulse RCB is made delayed 4 and becomes a transmission clock pulse SCB of the transmission circuit 1B of a telephone terminal B. The transmission data signal is transmitted from the circuit 1B to a controller 5 similarly.
JP12070780A 1980-09-02 1980-09-02 Time division full duplex communication system Pending JPS5745751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12070780A JPS5745751A (en) 1980-09-02 1980-09-02 Time division full duplex communication system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12070780A JPS5745751A (en) 1980-09-02 1980-09-02 Time division full duplex communication system

Publications (1)

Publication Number Publication Date
JPS5745751A true JPS5745751A (en) 1982-03-15

Family

ID=14792995

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12070780A Pending JPS5745751A (en) 1980-09-02 1980-09-02 Time division full duplex communication system

Country Status (1)

Country Link
JP (1) JPS5745751A (en)

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