JPS5748122A - Assignment controlling system of common input-output device - Google Patents

Assignment controlling system of common input-output device

Info

Publication number
JPS5748122A
JPS5748122A JP12224280A JP12224280A JPS5748122A JP S5748122 A JPS5748122 A JP S5748122A JP 12224280 A JP12224280 A JP 12224280A JP 12224280 A JP12224280 A JP 12224280A JP S5748122 A JPS5748122 A JP S5748122A
Authority
JP
Japan
Prior art keywords
output device
common input
cpu
line
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12224280A
Other languages
Japanese (ja)
Inventor
Tatsuo Sunochi
Shigenori Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12224280A priority Critical patent/JPS5748122A/en
Publication of JPS5748122A publication Critical patent/JPS5748122A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To omit an assignment controlling process for assigning a common input/ output device to a CPU, by providing a register for displaying the fact that it is requested to use the common input/output device. CONSTITUTION:At first, when a CPU 11-0 requests to use a common input/output device 12, its use request display bit alphao in a register 21 is attained to ''1'' through a line L5. On the other hand, a main CPU 11-1 monitors the register 21 periodically through a line L7, and detects the display bit alphao being ''1''. This information is fetched through a line L6, the CPU 11-1 checks whether the device 12 should be transferred to the CPU 10 or not, and when it should be transferred, a use permission display bit betao is rewritten to ''1''. The CPU 11-0 monitors periodically through the line L5 whether beta0 has become ''1'' or not, and fetches this ''1'' through a line L4, and after that, the common input/output device 12 is occupied.
JP12224280A 1980-09-05 1980-09-05 Assignment controlling system of common input-output device Pending JPS5748122A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12224280A JPS5748122A (en) 1980-09-05 1980-09-05 Assignment controlling system of common input-output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12224280A JPS5748122A (en) 1980-09-05 1980-09-05 Assignment controlling system of common input-output device

Publications (1)

Publication Number Publication Date
JPS5748122A true JPS5748122A (en) 1982-03-19

Family

ID=14831102

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12224280A Pending JPS5748122A (en) 1980-09-05 1980-09-05 Assignment controlling system of common input-output device

Country Status (1)

Country Link
JP (1) JPS5748122A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224346A (en) * 1985-07-24 1987-02-02 Hitachi Ltd Display controller and microcomputer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6224346A (en) * 1985-07-24 1987-02-02 Hitachi Ltd Display controller and microcomputer system

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