JPS5748233A - Exposure system for semiconductor substance - Google Patents

Exposure system for semiconductor substance

Info

Publication number
JPS5748233A
JPS5748233A JP55123536A JP12353680A JPS5748233A JP S5748233 A JPS5748233 A JP S5748233A JP 55123536 A JP55123536 A JP 55123536A JP 12353680 A JP12353680 A JP 12353680A JP S5748233 A JPS5748233 A JP S5748233A
Authority
JP
Japan
Prior art keywords
test pattern
pattern
reticle
shutter
exposure system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55123536A
Other languages
Japanese (ja)
Inventor
Masatoshi Imai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55123536A priority Critical patent/JPS5748233A/en
Publication of JPS5748233A publication Critical patent/JPS5748233A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70058—Mask illumination systems
    • G03F7/70066—Size and form of the illuminated area in the mask plane, e.g. reticle masking blades or blinds
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To highten productivity, by controlling exposure of a test pattern using a shutter when reduction-exposing a reticle having an element pattern as well as a test pattern. CONSTITUTION:When reduction-exposing a semiconducotor wafer using a reticle having a test pattern 3a and an element pattern 3b, element patterns are exposed by turns in a state of screened test pattern using a shutter screening a test pattern to expose simultaneously the test pattern and the following element pattern by opening the shutter at a fixed position. Thereby exposure can be performed with good productivity without exchanging the reticle.
JP55123536A 1980-09-08 1980-09-08 Exposure system for semiconductor substance Pending JPS5748233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55123536A JPS5748233A (en) 1980-09-08 1980-09-08 Exposure system for semiconductor substance

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55123536A JPS5748233A (en) 1980-09-08 1980-09-08 Exposure system for semiconductor substance

Publications (1)

Publication Number Publication Date
JPS5748233A true JPS5748233A (en) 1982-03-19

Family

ID=14863027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55123536A Pending JPS5748233A (en) 1980-09-08 1980-09-08 Exposure system for semiconductor substance

Country Status (1)

Country Link
JP (1) JPS5748233A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814137A (en) * 1981-07-16 1983-01-26 Fujitsu Ltd Exposure system by reduced projection
JPS59101830A (en) * 1982-12-01 1984-06-12 Canon Inc Printing and exposure device for semiconductor
JPS62109590A (en) * 1985-09-25 1987-05-20 ブラウン、アクチエンゲゼルシヤフト Cutter block for drying type razor
DE102004008835A1 (en) * 2004-02-20 2005-09-08 Infineon Technologies Ag Process for photolithographically exposing a semiconductor wafer used in the production of semiconductor circuits comprises carrying out lithographic exposure using a lithographic mask and post-exposing the wafer in the substrate region

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814137A (en) * 1981-07-16 1983-01-26 Fujitsu Ltd Exposure system by reduced projection
JPS59101830A (en) * 1982-12-01 1984-06-12 Canon Inc Printing and exposure device for semiconductor
JPS62109590A (en) * 1985-09-25 1987-05-20 ブラウン、アクチエンゲゼルシヤフト Cutter block for drying type razor
DE102004008835A1 (en) * 2004-02-20 2005-09-08 Infineon Technologies Ag Process for photolithographically exposing a semiconductor wafer used in the production of semiconductor circuits comprises carrying out lithographic exposure using a lithographic mask and post-exposing the wafer in the substrate region

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