JPS5748814A - Muting circuit for pulse width modulation amplifying system - Google Patents

Muting circuit for pulse width modulation amplifying system

Info

Publication number
JPS5748814A
JPS5748814A JP12428880A JP12428880A JPS5748814A JP S5748814 A JPS5748814 A JP S5748814A JP 12428880 A JP12428880 A JP 12428880A JP 12428880 A JP12428880 A JP 12428880A JP S5748814 A JPS5748814 A JP S5748814A
Authority
JP
Japan
Prior art keywords
muting
pulse width
width modulation
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12428880A
Other languages
Japanese (ja)
Inventor
Yoshiro Kunugi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Corp
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Corp, Pioneer Electronic Corp filed Critical Pioneer Corp
Priority to JP12428880A priority Critical patent/JPS5748814A/en
Publication of JPS5748814A publication Critical patent/JPS5748814A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/34—Muting amplifier when no signal is present

Landscapes

  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To suppress the pop sound low with high speed operation, by providing a switching means for muting which interrupts the transmission of a pulse train signal to the next stage on an output line of a pulse width modulator. CONSTITUTION:Between an output line 21 of a pulse width modulator 2 and ground, a muting circuit consisting of switching transistors (TR) Q1-Q3 is provided. When a muting signal to the base of the TRQ1 is at a low level, the TRs Q1-Q3 are turned off, and the output pulse train signal of the modulator 2 is transmitted to a pulse width modulation amplifier. When the muting signal is at high level, the TRQ1 turns on and the emitter current flows to the base of the TRQ3 via the TRQ2 to turn on the TRQ3 and to clamp the line 21 to ground potential. Thus, no pulse train signal is supplied to the next stage pulse width modulation amplifier for muting. Since the circuit 6 consists of an electronic circuit, the speed is high, and since the muting is not made at the input side of the circuit 2, pop sound can be suppressed lower.
JP12428880A 1980-09-08 1980-09-08 Muting circuit for pulse width modulation amplifying system Pending JPS5748814A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12428880A JPS5748814A (en) 1980-09-08 1980-09-08 Muting circuit for pulse width modulation amplifying system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12428880A JPS5748814A (en) 1980-09-08 1980-09-08 Muting circuit for pulse width modulation amplifying system

Publications (1)

Publication Number Publication Date
JPS5748814A true JPS5748814A (en) 1982-03-20

Family

ID=14881621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12428880A Pending JPS5748814A (en) 1980-09-08 1980-09-08 Muting circuit for pulse width modulation amplifying system

Country Status (1)

Country Link
JP (1) JPS5748814A (en)

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