JPS5752152A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5752152A
JPS5752152A JP55128257A JP12825780A JPS5752152A JP S5752152 A JPS5752152 A JP S5752152A JP 55128257 A JP55128257 A JP 55128257A JP 12825780 A JP12825780 A JP 12825780A JP S5752152 A JPS5752152 A JP S5752152A
Authority
JP
Japan
Prior art keywords
welding
seam
ring
profile
welding ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55128257A
Other languages
Japanese (ja)
Inventor
Koji Horiuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55128257A priority Critical patent/JPS5752152A/en
Publication of JPS5752152A publication Critical patent/JPS5752152A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/60—Seals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To preferably seal by welding a seam welded sealed semiconductor device formed by seam welding a metal cap on a laminated ceramic package and to airtightly hold the device by forming the profile of the metal cap analogous in shape but smaller in size than the profile of the welding ring. CONSTITUTION:After a welding ring 5 and an external lead 4 are soldered to a laminated ceramic 2, a semiconductor element is associated with a laminate ceramic package formed by plating nickel as primary layer and gold 8 on a mount 7, a bonding part 6, a welding ring 5 and an external lead 4. Then, the throttled part of a metallic cap 3' is engaged with the bore of the ring 5 to perform a seam welding. Since the profile of the welding ring is formed smaller than that of the metallic cap at this time, a gold-nickel alloy is obtained by seam weld sealing, with the result that airtightness is retained, and improper leakage can be remarkably reduced.
JP55128257A 1980-09-16 1980-09-16 Semiconductor device Pending JPS5752152A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55128257A JPS5752152A (en) 1980-09-16 1980-09-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55128257A JPS5752152A (en) 1980-09-16 1980-09-16 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5752152A true JPS5752152A (en) 1982-03-27

Family

ID=14980374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55128257A Pending JPS5752152A (en) 1980-09-16 1980-09-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5752152A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098176A3 (en) * 1982-06-30 1985-09-25 Fujitsu Limited The packaging of semiconductor chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0098176A3 (en) * 1982-06-30 1985-09-25 Fujitsu Limited The packaging of semiconductor chips

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