JPS575421A - Analog delay circuit - Google Patents

Analog delay circuit

Info

Publication number
JPS575421A
JPS575421A JP8000580A JP8000580A JPS575421A JP S575421 A JPS575421 A JP S575421A JP 8000580 A JP8000580 A JP 8000580A JP 8000580 A JP8000580 A JP 8000580A JP S575421 A JPS575421 A JP S575421A
Authority
JP
Japan
Prior art keywords
period
delay
signal
taps
capacitors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8000580A
Other languages
Japanese (ja)
Inventor
Mitsuo Tsunoishi
Seiji Kato
Norio Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8000580A priority Critical patent/JPS575421A/en
Publication of JPS575421A publication Critical patent/JPS575421A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/26—Time-delay networks

Landscapes

  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To use only one operational amplifier, independently of the number of stages of delay, by making time division for the signal transfer. CONSTITUTION:A signal is inputted from an IN terminal and outputted from taps 1-6 with 1T-6T (where; T is a unit delay time) of delay. Each switch SW0-5 is conductive when clock pulses are at high level and interrupted when at low level. Thus, taking the clock pulse 0 as a reference, clock pulses are at high level in the order of 0, 1, 2...5 at one period T, and the switches SW0, SW1...SW5 are correspondingly conductive. That is, the charge of capacitors C2-C6 is shifted right in time division during the period T and a new input signal is fetched to a capacitor C1. When the operation of one period is finished, an analog input signal different from the time by one period T respectively to the capacitors C1-C6. This signal is picked up via a buffer from the taps 1-6 at each delay.
JP8000580A 1980-06-13 1980-06-13 Analog delay circuit Pending JPS575421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8000580A JPS575421A (en) 1980-06-13 1980-06-13 Analog delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8000580A JPS575421A (en) 1980-06-13 1980-06-13 Analog delay circuit

Publications (1)

Publication Number Publication Date
JPS575421A true JPS575421A (en) 1982-01-12

Family

ID=13706208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8000580A Pending JPS575421A (en) 1980-06-13 1980-06-13 Analog delay circuit

Country Status (1)

Country Link
JP (1) JPS575421A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58138740A (en) * 1982-02-15 1983-08-17 Denki Kagaku Kogyo Kk Resin composition
EP0607630A1 (en) * 1992-12-15 1994-07-27 Philips Patentverwaltung GmbH Circuit for delaying a useful signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58138740A (en) * 1982-02-15 1983-08-17 Denki Kagaku Kogyo Kk Resin composition
EP0607630A1 (en) * 1992-12-15 1994-07-27 Philips Patentverwaltung GmbH Circuit for delaying a useful signal

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