JPS5757360A - Processing system of overflow - Google Patents

Processing system of overflow

Info

Publication number
JPS5757360A
JPS5757360A JP55109638A JP10963880A JPS5757360A JP S5757360 A JPS5757360 A JP S5757360A JP 55109638 A JP55109638 A JP 55109638A JP 10963880 A JP10963880 A JP 10963880A JP S5757360 A JPS5757360 A JP S5757360A
Authority
JP
Japan
Prior art keywords
overflow
register
contents
result
addition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55109638A
Other languages
Japanese (ja)
Inventor
Toshio Imai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu General Ltd
Aerojet Rocketdyne Holdings Inc
Original Assignee
Fujitsu General Ltd
Gencorp Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu General Ltd, Gencorp Inc filed Critical Fujitsu General Ltd
Priority to JP55109638A priority Critical patent/JPS5757360A/en
Publication of JPS5757360A publication Critical patent/JPS5757360A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49905—Exception handling
    • G06F7/4991—Overflow or underflow

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Calculators And Similar Devices (AREA)

Abstract

PURPOSE:To eliminate the recalculation back to the first stage for an electronic computer incorporating a printer, by printing the result of addition carried out immediately before an overflow with use of an overflow signal if the overflow is caused during an adding arithmetic. CONSTITUTION:When the addition key on a keyboard 4 is pushed, the contents of a figure register 1 is added with the contents of a result register 2 through adding/ subtracting circuit 8. The result of this addition is stored in the register 2, at the same time the occurrence of an overflow is checked through a deciding circuit 10. When an overflow is decided, a subtraction is indicated to an addition/ subtraction deciding circuit 9 by the overflow signal. Then the contents of the register 1 is subtracted from the contents of the register 2 through the circuit 8. And the result of calculation carried immediately before the overflow is printed by a printer 7. After this, the arithmetic function is stopped, and at the same time the printing action is locked up.
JP55109638A 1980-08-09 1980-08-09 Processing system of overflow Pending JPS5757360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55109638A JPS5757360A (en) 1980-08-09 1980-08-09 Processing system of overflow

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55109638A JPS5757360A (en) 1980-08-09 1980-08-09 Processing system of overflow

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP7599674A Division JPS546339B2 (en) 1974-07-02 1974-07-02

Publications (1)

Publication Number Publication Date
JPS5757360A true JPS5757360A (en) 1982-04-06

Family

ID=14515353

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55109638A Pending JPS5757360A (en) 1980-08-09 1980-08-09 Processing system of overflow

Country Status (1)

Country Link
JP (1) JPS5757360A (en)

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