JPS5758206A - Address circuit of memory - Google Patents

Address circuit of memory

Info

Publication number
JPS5758206A
JPS5758206A JP55132873A JP13287380A JPS5758206A JP S5758206 A JPS5758206 A JP S5758206A JP 55132873 A JP55132873 A JP 55132873A JP 13287380 A JP13287380 A JP 13287380A JP S5758206 A JPS5758206 A JP S5758206A
Authority
JP
Japan
Prior art keywords
address
readout
memory
write
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55132873A
Other languages
Japanese (ja)
Other versions
JPH0232702B2 (en
Inventor
Hiromichi Tanaka
Takashi Hoshino
Shoji Ueno
Harukuni Kohari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Victor Company of Japan Ltd
Nippon Victor KK
Original Assignee
Hitachi Ltd
Victor Company of Japan Ltd
Nippon Victor KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Victor Company of Japan Ltd, Nippon Victor KK filed Critical Hitachi Ltd
Priority to JP55132873A priority Critical patent/JPS5758206A/en
Publication of JPS5758206A publication Critical patent/JPS5758206A/en
Publication of JPH0232702B2 publication Critical patent/JPH0232702B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To prevent an address of a memory from becoming unstable when the electric power supply is turned on, etc., by loading a value of a readout side address counter to a write address counter at every 2 vertical synchronizing sections (2V). CONSTITUTION:Outputs of counters 7, 8 for setting an address of each readout and write side memory add a constant value to a write address through a multiplexing circuit 9, and are supplied to an adding circuit 11 for interleave to a readout address. To this circuit 11, an ROM data is provided from an ROM10. An output of this circuit 11 becomes an address of a memory 12. On the other hand, a load pulse 15 which is generated by one at every 2V is provided to a load terminal of the address counter 8. In this way, the counter 8 becomes the same value as the readout address counter 7 and starts counting after the pulse 15 has been provided, therefore, the write and readout memories are not overlapped. According to such constitution, it is prevented that an address of the memory becomes unstable.
JP55132873A 1980-09-26 1980-09-26 Address circuit of memory Granted JPS5758206A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55132873A JPS5758206A (en) 1980-09-26 1980-09-26 Address circuit of memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55132873A JPS5758206A (en) 1980-09-26 1980-09-26 Address circuit of memory

Publications (2)

Publication Number Publication Date
JPS5758206A true JPS5758206A (en) 1982-04-07
JPH0232702B2 JPH0232702B2 (en) 1990-07-23

Family

ID=15091542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55132873A Granted JPS5758206A (en) 1980-09-26 1980-09-26 Address circuit of memory

Country Status (1)

Country Link
JP (1) JPS5758206A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024307U (en) * 1983-07-26 1985-02-19 株式会社クボタ Sedimentation thickener tank
US5297100A (en) * 1991-09-28 1994-03-22 Samsung Electronics Co., Ltd. Address control system for a RAM in a digital audio set

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52102013A (en) * 1976-02-24 1977-08-26 Sony Corp Memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52102013A (en) * 1976-02-24 1977-08-26 Sony Corp Memory unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024307U (en) * 1983-07-26 1985-02-19 株式会社クボタ Sedimentation thickener tank
US5297100A (en) * 1991-09-28 1994-03-22 Samsung Electronics Co., Ltd. Address control system for a RAM in a digital audio set

Also Published As

Publication number Publication date
JPH0232702B2 (en) 1990-07-23

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