JPS5760512A - Data separation circuit - Google Patents

Data separation circuit

Info

Publication number
JPS5760512A
JPS5760512A JP13293580A JP13293580A JPS5760512A JP S5760512 A JPS5760512 A JP S5760512A JP 13293580 A JP13293580 A JP 13293580A JP 13293580 A JP13293580 A JP 13293580A JP S5760512 A JPS5760512 A JP S5760512A
Authority
JP
Japan
Prior art keywords
data separation
circuit
vtr
level
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13293580A
Other languages
Japanese (ja)
Inventor
Takaharu Noguchi
Isao Akitake
Takao Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13293580A priority Critical patent/JPS5760512A/en
Publication of JPS5760512A publication Critical patent/JPS5760512A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10527—Audio or video recording; Data buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Digital Magnetic Recording (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To set an optimum data separation level in a PCM encoder/decoder automatically using a home use VTR, by forming the data separation level based on the pedestal fixed to a constant voltage. CONSTITUTION:After a reproduction video signal 9 from a VTR is made to a prescribed amplitude level at an AGC amplifying circuit 23, it is applied to a pedestal clamp circuit 24. A pedestal signal clamped to a prescribed voltage at the clamp circuit 24 is inputted to a data separation comparator 11 and to a data separation level detection circuit 28. After the circuit 28 halves the amplitude level of data, it gives a rectified voltage to the comparator 11 as a comparison voltage. Thus, the optimum data separation level of a tape can be set automatically independently of types of the VTR.
JP13293580A 1980-09-26 1980-09-26 Data separation circuit Pending JPS5760512A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13293580A JPS5760512A (en) 1980-09-26 1980-09-26 Data separation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13293580A JPS5760512A (en) 1980-09-26 1980-09-26 Data separation circuit

Publications (1)

Publication Number Publication Date
JPS5760512A true JPS5760512A (en) 1982-04-12

Family

ID=15092933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13293580A Pending JPS5760512A (en) 1980-09-26 1980-09-26 Data separation circuit

Country Status (1)

Country Link
JP (1) JPS5760512A (en)

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