JPS5764312A - Synchronizing signal circuit - Google Patents

Synchronizing signal circuit

Info

Publication number
JPS5764312A
JPS5764312A JP14020080A JP14020080A JPS5764312A JP S5764312 A JPS5764312 A JP S5764312A JP 14020080 A JP14020080 A JP 14020080A JP 14020080 A JP14020080 A JP 14020080A JP S5764312 A JPS5764312 A JP S5764312A
Authority
JP
Japan
Prior art keywords
signal
synchronizing signal
synchronizing
frequency
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14020080A
Other languages
Japanese (ja)
Inventor
Yukihiko Haikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ARUPAIN KK
Alpine Electronics Inc
Original Assignee
ARUPAIN KK
Alpine Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ARUPAIN KK, Alpine Electronics Inc filed Critical ARUPAIN KK
Priority to JP14020080A priority Critical patent/JPS5764312A/en
Publication of JPS5764312A publication Critical patent/JPS5764312A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10527—Audio or video recording; Data buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE:To obtain a synchronizing signal by frequency-dividing a clock signal which is an integral multiple of a horizontal synchronizing signal, through the detection of ends of a signal outputted from the synchronizing separation circuit such as PCM processor from a clear pulse by muting. CONSTITUTION:A signal outputted from a synchronizing separation circuit 11 is introduced to a differentiation circuit of an edge detection circuit 12, and the output (b) is inputted to a monostable multivibrator M via an NOR gate G, then a horizontal synchronizing signal to noise is muted, and when the output (d) is inputted to the differentiation circuit, a clear pulse is obtained. On the other hand, a clock signal outputted from a signal generating circuit 13 forming the clock signal which is an integral multiple of a horizontal synchronizing signal f0 is frequency-divided while being cleared with a clear pulse at a frequency divider 14 and 42 frequency- division and sequentially at frequency dividers 15, 16. Thus, noise is rejected, dropped-out synchronizing signal is replenished, and a synchronizing signal which is almost in synchronizing with the playback synchronizing signal without delay time can be obtained.
JP14020080A 1980-10-07 1980-10-07 Synchronizing signal circuit Pending JPS5764312A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14020080A JPS5764312A (en) 1980-10-07 1980-10-07 Synchronizing signal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14020080A JPS5764312A (en) 1980-10-07 1980-10-07 Synchronizing signal circuit

Publications (1)

Publication Number Publication Date
JPS5764312A true JPS5764312A (en) 1982-04-19

Family

ID=15263236

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14020080A Pending JPS5764312A (en) 1980-10-07 1980-10-07 Synchronizing signal circuit

Country Status (1)

Country Link
JP (1) JPS5764312A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6070556A (en) * 1983-09-28 1985-04-22 Canon Inc Information recording and reproducing device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4831011A (en) * 1971-08-25 1973-04-24
JPS54151812A (en) * 1978-05-22 1979-11-29 Nec Corp Variable frequency oscillating circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4831011A (en) * 1971-08-25 1973-04-24
JPS54151812A (en) * 1978-05-22 1979-11-29 Nec Corp Variable frequency oscillating circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6070556A (en) * 1983-09-28 1985-04-22 Canon Inc Information recording and reproducing device

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