JPS5764962A - Semiconductor integrated circuit device and its manufacture - Google Patents

Semiconductor integrated circuit device and its manufacture

Info

Publication number
JPS5764962A
JPS5764962A JP55141217A JP14121780A JPS5764962A JP S5764962 A JPS5764962 A JP S5764962A JP 55141217 A JP55141217 A JP 55141217A JP 14121780 A JP14121780 A JP 14121780A JP S5764962 A JPS5764962 A JP S5764962A
Authority
JP
Japan
Prior art keywords
substrate
defect layer
well
defects
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55141217A
Other languages
Japanese (ja)
Inventor
Masahide Sugano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55141217A priority Critical patent/JPS5764962A/en
Publication of JPS5764962A publication Critical patent/JPS5764962A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To shorten remarkably the life of minority carrier in damaged layer by plural crystal defects to prevent latching up and to adsorb defects in the surface of a substrate to be removed in a semiconductor integrated circuir device by a method wherein the damaged layers are introduced intentionally in the N type Si substrate and a P-well respectively. CONSTITUTION:The high density defect layer 31 in the substrate exists extensively under a P channel MOSFET5, and the high density defect layer 32 in the P-well is arranged extensively under an N channel MOSFET6. Holes implanted in the N type substrate 1 from a source 5S of the FET5 recombine in the defect layer 31, and electrons implanted in the P-well 2 from the FET6 recombine in the defect layer 32. Accordingly actions of a lateral PNP transistor 21, a vertical NPN transistor 22 being parasitic in this device are restricted, latching up is prevented and at the same time fine defects in the surface are removed, and the C-MOSIC having high reliability can be obtained.
JP55141217A 1980-10-09 1980-10-09 Semiconductor integrated circuit device and its manufacture Pending JPS5764962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55141217A JPS5764962A (en) 1980-10-09 1980-10-09 Semiconductor integrated circuit device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55141217A JPS5764962A (en) 1980-10-09 1980-10-09 Semiconductor integrated circuit device and its manufacture

Publications (1)

Publication Number Publication Date
JPS5764962A true JPS5764962A (en) 1982-04-20

Family

ID=15286853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55141217A Pending JPS5764962A (en) 1980-10-09 1980-10-09 Semiconductor integrated circuit device and its manufacture

Country Status (1)

Country Link
JP (1) JPS5764962A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984461A (en) * 1982-11-05 1984-05-16 Hitachi Ltd semiconductor equipment
JPS59117153A (en) * 1982-12-10 1984-07-06 ゼネラル・エレクトリック・カンパニイ Semiconductor device and method of producing same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984461A (en) * 1982-11-05 1984-05-16 Hitachi Ltd semiconductor equipment
JPS59117153A (en) * 1982-12-10 1984-07-06 ゼネラル・エレクトリック・カンパニイ Semiconductor device and method of producing same

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