JPS5771044A - Data buffer control system - Google Patents

Data buffer control system

Info

Publication number
JPS5771044A
JPS5771044A JP14782580A JP14782580A JPS5771044A JP S5771044 A JPS5771044 A JP S5771044A JP 14782580 A JP14782580 A JP 14782580A JP 14782580 A JP14782580 A JP 14782580A JP S5771044 A JPS5771044 A JP S5771044A
Authority
JP
Japan
Prior art keywords
data
byte
same time
read
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14782580A
Other languages
Japanese (ja)
Inventor
Masao Koyabu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14782580A priority Critical patent/JPS5771044A/en
Publication of JPS5771044A publication Critical patent/JPS5771044A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/04—Addressing variable-length words or parts of words

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To eliminate the need for an aligning circuit for data, by generating transfer data starting addresses at an optional byte boundary in a control circuit for a data buffer wherein the transfer data is stored temporarily. CONSTITUTION:Write address registers WA0-WA1, a read address register RA, and (m) units of (n)-byte-width data buffers DB0-DB3 which can be accessed with mutually different at the same time are equipped. When (n)-byte data is written, the (n)-byte data is written in different addresses of the (m) buffer memories at the same time, and when (mXn)-byte data is read, the (mXn)-byte data is read from the same addresses of the (m) buffer memories at the same time. Therefore, transfer data starting at an optional type boundary is generated without providing a byte aligning means.
JP14782580A 1980-10-22 1980-10-22 Data buffer control system Pending JPS5771044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14782580A JPS5771044A (en) 1980-10-22 1980-10-22 Data buffer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14782580A JPS5771044A (en) 1980-10-22 1980-10-22 Data buffer control system

Publications (1)

Publication Number Publication Date
JPS5771044A true JPS5771044A (en) 1982-05-01

Family

ID=15439077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14782580A Pending JPS5771044A (en) 1980-10-22 1980-10-22 Data buffer control system

Country Status (1)

Country Link
JP (1) JPS5771044A (en)

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