JPS577161A - Mos semiconductor device - Google Patents

Mos semiconductor device

Info

Publication number
JPS577161A
JPS577161A JP8015980A JP8015980A JPS577161A JP S577161 A JPS577161 A JP S577161A JP 8015980 A JP8015980 A JP 8015980A JP 8015980 A JP8015980 A JP 8015980A JP S577161 A JPS577161 A JP S577161A
Authority
JP
Japan
Prior art keywords
buried insulating
substrate
drain
prevented
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8015980A
Other languages
English (en)
Inventor
Yutaka Hatano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP8015980A priority Critical patent/JPS577161A/ja
Priority to EP81104511A priority patent/EP0042552B1/en
Priority to DE8181104511T priority patent/DE3172418D1/de
Publication of JPS577161A publication Critical patent/JPS577161A/ja
Priority to US06/596,561 priority patent/US4571609A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0278Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline channels on wafers after forming insulating device isolations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6704Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6708Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing the kink effect or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113Isolations within a component, i.e. internal isolations
    • H10D62/115Dielectric isolations, e.g. air gaps
    • H10D62/116Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/856Complementary IGFETs, e.g. CMOS the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices
    • H10D88/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/061Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01Manufacture or treatment
    • H10W10/021Manufacture or treatment of air gaps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20Air gaps
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/901MOSFET substrate bias

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
JP8015980A 1980-06-16 1980-06-16 Mos semiconductor device Pending JPS577161A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP8015980A JPS577161A (en) 1980-06-16 1980-06-16 Mos semiconductor device
EP81104511A EP0042552B1 (en) 1980-06-16 1981-06-11 Mos type semiconductor device
DE8181104511T DE3172418D1 (en) 1980-06-16 1981-06-11 Mos type semiconductor device
US06/596,561 US4571609A (en) 1980-06-16 1984-04-03 Stacked MOS device with means to prevent substrate floating

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8015980A JPS577161A (en) 1980-06-16 1980-06-16 Mos semiconductor device

Publications (1)

Publication Number Publication Date
JPS577161A true JPS577161A (en) 1982-01-14

Family

ID=13710517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8015980A Pending JPS577161A (en) 1980-06-16 1980-06-16 Mos semiconductor device

Country Status (4)

Country Link
US (1) US4571609A (ja)
EP (1) EP0042552B1 (ja)
JP (1) JPS577161A (ja)
DE (1) DE3172418D1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61502922A (ja) * 1984-08-01 1986-12-11 アメリカン テレフオン アンド テレグラフ カムパニ− 絶縁体上の半導体(soi)デバイス及びsoi ic製作法
JPS6235668A (ja) * 1985-08-09 1987-02-16 Nec Corp 半導体記憶装置
US7449375B2 (en) 2003-03-17 2008-11-11 Kabushiki Kaisha Toshiba Fin semiconductor device and method for fabricating the same

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4637127A (en) * 1981-07-07 1987-01-20 Nippon Electric Co., Ltd. Method for manufacturing a semiconductor device
JPS5890769A (ja) * 1981-11-25 1983-05-30 Mitsubishi Electric Corp 積層半導体装置
JPS60501927A (ja) * 1983-07-25 1985-11-07 アメリカン テレフオン アンド テレグラフ カムパニ− 浅い接合の半導体デバイス
US4611220A (en) * 1983-11-16 1986-09-09 General Motors Corporation Junction-MOS power field effect transistor
US4763183A (en) * 1984-08-01 1988-08-09 American Telephone And Telegraph Co., At&T Bell Laboratories Semiconductor-on-insulator (SOI) devices and SOI IC fabrication method
US6372596B1 (en) * 1985-01-30 2002-04-16 Texas Instruments Incorporated Method of making horizontal bipolar transistor with insulated base structure
US4683637A (en) * 1986-02-07 1987-08-04 Motorola, Inc. Forming depthwise isolation by selective oxygen/nitrogen deep implant and reaction annealing
US4862232A (en) * 1986-09-22 1989-08-29 General Motors Corporation Transistor structure for high temperature logic circuits with insulation around source and drain regions
US4797718A (en) * 1986-12-08 1989-01-10 Delco Electronics Corporation Self-aligned silicon MOS device
US4714685A (en) * 1986-12-08 1987-12-22 General Motors Corporation Method of fabricating self-aligned silicon-on-insulator like devices
US4716128A (en) * 1986-12-10 1987-12-29 General Motors Corporation Method of fabricating silicon-on-insulator like devices
US4749441A (en) * 1986-12-11 1988-06-07 General Motors Corporation Semiconductor mushroom structure fabrication
US4786608A (en) * 1986-12-30 1988-11-22 Harris Corp. Technique for forming electric field shielding layer in oxygen-implanted silicon substrate
US4910564A (en) * 1987-07-01 1990-03-20 Mitsubishi Denki Kabushiki Kaisha Highly integrated field effect transistor and method for manufacturing the same
US5194749A (en) * 1987-11-30 1993-03-16 Hitachi, Ltd. Semiconductor integrated circuit device
SE464949B (sv) * 1989-11-09 1991-07-01 Asea Brown Boveri Halvledarswitch
DE69213539T2 (de) * 1991-04-26 1997-02-20 Canon Kk Halbleitervorrichtung mit verbessertem isoliertem Gate-Transistor
USH1435H (en) * 1991-10-21 1995-05-02 Cherne Richard D SOI CMOS device having body extension for providing sidewall channel stop and bodytie
WO1993020587A1 (en) * 1992-03-30 1993-10-14 Honeywell Inc. Mos structure for reducing snapback
SE513283C2 (sv) * 1996-07-26 2000-08-14 Ericsson Telefon Ab L M MOS-transistorstruktur med utsträckt driftregion
US5913135A (en) * 1996-12-19 1999-06-15 Texas Instruments Incorporated Method for forming planar field effect transistors with source and drain on oxide and device constructed therefrom
DE29815070U1 (de) 1998-08-25 1999-02-11 W. Willpütz Kunststoffverarbeitungsgesellschaft mbH, 50996 Köln Wäschebügel mit federnder Fixierzunge
US6228779B1 (en) 1998-11-06 2001-05-08 Novellus Systems, Inc. Ultra thin oxynitride and nitride/oxide stacked gate dielectrics fabricated by high pressure technology
US6150834A (en) * 1998-11-12 2000-11-21 International Business Machines Corporation Elimination of SOI parasitic bipolar effect
FR2791178B1 (fr) * 1999-03-19 2001-11-16 France Telecom NOUVEAU DISPOSITIF SEMI-CONDUCTEUR COMBINANT LES AVANTAGES DES ARCHITECTURES MASSIVE ET soi, ET PROCEDE DE FABRICATION
US6245636B1 (en) 1999-10-20 2001-06-12 Advanced Micro Devices, Inc. Method of formation of pseudo-SOI structures with direct contact of transistor body to the substrate
US6465852B1 (en) 1999-10-20 2002-10-15 Advanced Micro Devices, Inc. Silicon wafer including both bulk and SOI regions and method for forming same on a bulk silicon wafer
US6376286B1 (en) 1999-10-20 2002-04-23 Advanced Micro Devices, Inc. Field effect transistor with non-floating body and method for forming same on a bulk silicon wafer
US6514809B1 (en) 2000-11-03 2003-02-04 Advanced Micro Devices, Inc. SOI field effect transistors with body contacts formed by selective etch and fill
US6544874B2 (en) 2001-08-13 2003-04-08 International Business Machines Corporation Method for forming junction on insulator (JOI) structure
US6958516B2 (en) * 2004-01-08 2005-10-25 International Business Machines Corporation Discriminative SOI with oxide holes underneath DC source/drain
JP2008251646A (ja) * 2007-03-29 2008-10-16 Seiko Epson Corp 不揮発性半導体記憶装置およびその製造方法、半導体装置
FR2987699A1 (fr) * 2012-03-01 2013-09-06 St Microelectronics Sa Composant electronique realise sur un substrat fdsoi

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5236983A (en) * 1975-09-18 1977-03-22 Matsushita Electric Ind Co Ltd Mos type semiconductor integrated circuit device and process for produ ction of same

Family Cites Families (14)

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Publication number Priority date Publication date Assignee Title
US3600651A (en) * 1969-12-08 1971-08-17 Fairchild Camera Instr Co Bipolar and field-effect transistor using polycrystalline epitaxial deposited silicon
CA930477A (en) * 1971-12-22 1973-07-17 Microsystems International Limited Multi-level integrated circuit and fabrication thereof
JPS5279787A (en) * 1975-12-26 1977-07-05 Toshiba Corp Integrated circuit device
JPS54881A (en) * 1977-06-03 1979-01-06 Fujitsu Ltd Semiconductor device
JPS5721856B2 (en) * 1977-11-28 1982-05-10 Nippon Telegraph & Telephone Semiconductor and its manufacture
JPS5910581B2 (ja) * 1977-12-01 1984-03-09 富士通株式会社 半導体装置の製造方法
JPS5518052A (en) * 1978-07-25 1980-02-07 Mitsubishi Electric Corp Semiconductor laser modulator
JPS5543872A (en) * 1978-09-22 1980-03-27 Pioneer Electronic Corp Insulating gate field effect transistor
JPS5574172A (en) * 1978-11-27 1980-06-04 Mitsubishi Electric Corp Interpolation type mos transistor
JPS6015155B2 (ja) * 1978-12-30 1985-04-17 富士通株式会社 半導体装置の製造方法
US4272880A (en) * 1979-04-20 1981-06-16 Intel Corporation MOS/SOS Process
JPS5837949A (ja) * 1981-08-31 1983-03-05 Toshiba Corp 集積回路装置
JPS58164219A (ja) * 1982-03-25 1983-09-29 Agency Of Ind Science & Technol 積層型半導体装置の製造方法
US4476475A (en) * 1982-11-19 1984-10-09 Northern Telecom Limited Stacked MOS transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5236983A (en) * 1975-09-18 1977-03-22 Matsushita Electric Ind Co Ltd Mos type semiconductor integrated circuit device and process for produ ction of same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61502922A (ja) * 1984-08-01 1986-12-11 アメリカン テレフオン アンド テレグラフ カムパニ− 絶縁体上の半導体(soi)デバイス及びsoi ic製作法
JPS6235668A (ja) * 1985-08-09 1987-02-16 Nec Corp 半導体記憶装置
US7449375B2 (en) 2003-03-17 2008-11-11 Kabushiki Kaisha Toshiba Fin semiconductor device and method for fabricating the same

Also Published As

Publication number Publication date
DE3172418D1 (en) 1985-10-31
EP0042552A2 (en) 1981-12-30
EP0042552B1 (en) 1985-09-25
EP0042552A3 (en) 1982-05-05
US4571609A (en) 1986-02-18

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