JPS5772442A - Clock extracting circuit for data receiver - Google Patents

Clock extracting circuit for data receiver

Info

Publication number
JPS5772442A
JPS5772442A JP55147536A JP14753680A JPS5772442A JP S5772442 A JPS5772442 A JP S5772442A JP 55147536 A JP55147536 A JP 55147536A JP 14753680 A JP14753680 A JP 14753680A JP S5772442 A JPS5772442 A JP S5772442A
Authority
JP
Japan
Prior art keywords
switching signal
band switching
data group
pll1
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55147536A
Other languages
Japanese (ja)
Inventor
Yasushi Takeuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55147536A priority Critical patent/JPS5772442A/en
Publication of JPS5772442A publication Critical patent/JPS5772442A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To prevent a bit error rate from extending to the largest rate in the region of a high C/N, by detecting one bit synchronizing part for every data group to generate a band switching signal and preventing the bit synchronizing detection in the same group hereafter. CONSTITUTION:A bit synchronizing part BS of the first data in each data group is detected by a detecting circuit 2 to generate a band switching signal CS2. After the band switching signal CS2 is generated once, the detecting circuit 2 does not restart the detection operation for the bit synchronizing part BS until a time corresponding to a data group length N.L elapses by the function of a counter 10. A PLL1 is changed to the state of a high Q value when the band switching signal CS2 is generated once, and the PLL1 holds this state to output a clock pulse of a high stability. Even if the band switching signal is outputted erroneously by the influence of a noise or the like, the band switching signal is not outputted again for the same data group, and the PLL1 outputs the clock pulse of a high stability, thus preventing the bit error rate from extending to the largest rate.
JP55147536A 1980-10-23 1980-10-23 Clock extracting circuit for data receiver Pending JPS5772442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55147536A JPS5772442A (en) 1980-10-23 1980-10-23 Clock extracting circuit for data receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55147536A JPS5772442A (en) 1980-10-23 1980-10-23 Clock extracting circuit for data receiver

Publications (1)

Publication Number Publication Date
JPS5772442A true JPS5772442A (en) 1982-05-06

Family

ID=15432526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55147536A Pending JPS5772442A (en) 1980-10-23 1980-10-23 Clock extracting circuit for data receiver

Country Status (1)

Country Link
JP (1) JPS5772442A (en)

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