JPS5772476A - Processing circuit for video intermediate frequency signal - Google Patents

Processing circuit for video intermediate frequency signal

Info

Publication number
JPS5772476A
JPS5772476A JP55148924A JP14892480A JPS5772476A JP S5772476 A JPS5772476 A JP S5772476A JP 55148924 A JP55148924 A JP 55148924A JP 14892480 A JP14892480 A JP 14892480A JP S5772476 A JPS5772476 A JP S5772476A
Authority
JP
Japan
Prior art keywords
circuit
signal
sif
video
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55148924A
Other languages
Japanese (ja)
Inventor
Junichi Momotake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55148924A priority Critical patent/JPS5772476A/en
Publication of JPS5772476A publication Critical patent/JPS5772476A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/4446—IF amplifier circuits specially adapted for B&W TV

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Receiver Circuits (AREA)

Abstract

PURPOSE:To prevent the amplitude of a sound IF signal from being attenuated, by transmitting the output of a video IF amplifying circuit to a video detecting circuit through a buffer circuit and a sound IF trap circuit. CONSTITUTION:A VIF signal amplified by a video IF amplifying circuit and a sound IF signal SIF are led to a terminal 1. The signal SIF is led to a detecting circuit only for SIF from a terminal 2 as it is and is detected. Meanwhile, the VIF signal passes through a buffer circuit 5 and is sent to an SIF trap circuit 3, and the signal SIF is attenuated and is led from a terminal 4 to the video detecting circuit. Thus, the attenuation of the SIF signal appearing in the terminal 2 is prevented completely approximately by inserting the buffer circuit 5.
JP55148924A 1980-10-23 1980-10-23 Processing circuit for video intermediate frequency signal Pending JPS5772476A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55148924A JPS5772476A (en) 1980-10-23 1980-10-23 Processing circuit for video intermediate frequency signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55148924A JPS5772476A (en) 1980-10-23 1980-10-23 Processing circuit for video intermediate frequency signal

Publications (1)

Publication Number Publication Date
JPS5772476A true JPS5772476A (en) 1982-05-06

Family

ID=15463700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55148924A Pending JPS5772476A (en) 1980-10-23 1980-10-23 Processing circuit for video intermediate frequency signal

Country Status (1)

Country Link
JP (1) JPS5772476A (en)

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