JPS57729A - Multiple information processing system - Google Patents

Multiple information processing system

Info

Publication number
JPS57729A
JPS57729A JP7395980A JP7395980A JPS57729A JP S57729 A JPS57729 A JP S57729A JP 7395980 A JP7395980 A JP 7395980A JP 7395980 A JP7395980 A JP 7395980A JP S57729 A JPS57729 A JP S57729A
Authority
JP
Japan
Prior art keywords
loop
connection ports
output port
input port
troubled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7395980A
Other languages
Japanese (ja)
Other versions
JPS6112588B2 (en
Inventor
Tsuguo Matsuura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7395980A priority Critical patent/JPS57729A/en
Publication of JPS57729A publication Critical patent/JPS57729A/en
Publication of JPS6112588B2 publication Critical patent/JPS6112588B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To reconstitute a multiprocessor even when one CPU is troubled by providing each of CPUs, sharing a main storage device, with two pairs of input and output ports for a loop interface and by alternating the return flow directions of information in response to a control signal.
CONSTITUTION: Central processing units CPU0WCPU2 are connected in a loop and use a main storage device MS in common. In triple multiple operation, each CPU normally uses the connection ports of the input port I1 and output port O1 of a loop interface IF for operation to circulate information, required among the CPUs, in a loop shape. For example, if the CPU0 is troubled, the CPU1 uses the connection ports of the input port I2 and output port O1 of the loop IF by being switched by a system constitution controlling signal, and the CPU2 uses the connection ports of the input port I1 and output port O2, thereby circulating informatin between the CPU1 and CPU2 in the loop shape.
COPYRIGHT: (C)1982,JPO&Japio
JP7395980A 1980-06-02 1980-06-02 Multiple information processing system Granted JPS57729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7395980A JPS57729A (en) 1980-06-02 1980-06-02 Multiple information processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7395980A JPS57729A (en) 1980-06-02 1980-06-02 Multiple information processing system

Publications (2)

Publication Number Publication Date
JPS57729A true JPS57729A (en) 1982-01-05
JPS6112588B2 JPS6112588B2 (en) 1986-04-09

Family

ID=13533121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7395980A Granted JPS57729A (en) 1980-06-02 1980-06-02 Multiple information processing system

Country Status (1)

Country Link
JP (1) JPS57729A (en)

Also Published As

Publication number Publication date
JPS6112588B2 (en) 1986-04-09

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