JPS57732A - Interface device - Google Patents

Interface device

Info

Publication number
JPS57732A
JPS57732A JP7404880A JP7404880A JPS57732A JP S57732 A JPS57732 A JP S57732A JP 7404880 A JP7404880 A JP 7404880A JP 7404880 A JP7404880 A JP 7404880A JP S57732 A JPS57732 A JP S57732A
Authority
JP
Japan
Prior art keywords
data
terminal
computer
ram34
master computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7404880A
Other languages
Japanese (ja)
Inventor
Masayuki Kuroki
Mitsuo Ohashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KASHIWAGI KENKYUSHO KK
Original Assignee
KASHIWAGI KENKYUSHO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KASHIWAGI KENKYUSHO KK filed Critical KASHIWAGI KENKYUSHO KK
Priority to JP7404880A priority Critical patent/JPS57732A/en
Publication of JPS57732A publication Critical patent/JPS57732A/en
Pending legal-status Critical Current

Links

Landscapes

  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE: To connect an interface IF device without reference to the kind of an electronic computer and a manufactory by interposing an IC memory between a master electronic computer and a terminal equipment or subordinate electronic computer for reading and writing.
CONSTITUTION: To connect a terminal 33 to a master computer, a connector 27 is inserted into a memory IC connector on a memory card connected to the master computer. When data is written to the terminal 33 from the master computer, a signal is generated on the chip selection line 44 of an IF device 25 and a signal is sent from the master computer to an address line 41, a data line 42 and a control line 43 to write the data in an RAM34 via a gate buffer 38. An internal computer 46 monitors the RAM34 all the time and, when detecting the data being written in the RAM34, reads the data in the RAM34 via a gate buffer 39 to send the data to the terminal 33 via an input and output port 52. When the terminal is to send data to the master computer, the data is written in the RAM34 from the terminal in the opposite route and it is read by the master computer.
COPYRIGHT: (C)1982,JPO&Japio
JP7404880A 1980-06-02 1980-06-02 Interface device Pending JPS57732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7404880A JPS57732A (en) 1980-06-02 1980-06-02 Interface device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7404880A JPS57732A (en) 1980-06-02 1980-06-02 Interface device

Publications (1)

Publication Number Publication Date
JPS57732A true JPS57732A (en) 1982-01-05

Family

ID=13535897

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7404880A Pending JPS57732A (en) 1980-06-02 1980-06-02 Interface device

Country Status (1)

Country Link
JP (1) JPS57732A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024545543A (en) * 2022-10-12 2024-12-10 ルイジェ ネットワークス カンパニー,リミテッド Chip-to-module cable assembly and PCB board circuitry

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2024545543A (en) * 2022-10-12 2024-12-10 ルイジェ ネットワークス カンパニー,リミテッド Chip-to-module cable assembly and PCB board circuitry

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