JPS5773457A - Control system for electronic computer system - Google Patents

Control system for electronic computer system

Info

Publication number
JPS5773457A
JPS5773457A JP14761180A JP14761180A JPS5773457A JP S5773457 A JPS5773457 A JP S5773457A JP 14761180 A JP14761180 A JP 14761180A JP 14761180 A JP14761180 A JP 14761180A JP S5773457 A JPS5773457 A JP S5773457A
Authority
JP
Japan
Prior art keywords
common memory
area
memory areas
computer system
electronic computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14761180A
Other languages
Japanese (ja)
Inventor
Naoki Iwasaki
Masahiko Hida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14761180A priority Critical patent/JPS5773457A/en
Publication of JPS5773457A publication Critical patent/JPS5773457A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/524—Deadlock detection or avoidance

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To prevent an electronic computer system from the generation of dead lock by monitoring the using status or required contents of common memory areas with a monitoring program at a constant frequency and searching and releasing the prescribed common memory area. CONSTITUTION:A computer system 1 includes a common memory area 3 which can use both control processing programs 2a, 2b in common and the area 3 is divided into plural unit common memory areas. Usually, the programs 2a and 2b are controlled so as not to secure the area 3 simultaneously and the using status of the area is monitored by a monitoring program 5 at a constant frequency. At the generation of dead lock, the earliest request within the time when control processing program securing requests in waiting are outputted is searched and the number of unit common memory area is checked. Continuous common memory areas sufficiently required for securing the number of requests are searched from the common memory areas at use and released.
JP14761180A 1980-10-23 1980-10-23 Control system for electronic computer system Pending JPS5773457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14761180A JPS5773457A (en) 1980-10-23 1980-10-23 Control system for electronic computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14761180A JPS5773457A (en) 1980-10-23 1980-10-23 Control system for electronic computer system

Publications (1)

Publication Number Publication Date
JPS5773457A true JPS5773457A (en) 1982-05-08

Family

ID=15434232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14761180A Pending JPS5773457A (en) 1980-10-23 1980-10-23 Control system for electronic computer system

Country Status (1)

Country Link
JP (1) JPS5773457A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03246730A (en) * 1990-02-26 1991-11-05 Fujitsu Ltd Deadlock state detection control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03246730A (en) * 1990-02-26 1991-11-05 Fujitsu Ltd Deadlock state detection control system

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