JPS5773942A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5773942A
JPS5773942A JP55150354A JP15035480A JPS5773942A JP S5773942 A JPS5773942 A JP S5773942A JP 55150354 A JP55150354 A JP 55150354A JP 15035480 A JP15035480 A JP 15035480A JP S5773942 A JPS5773942 A JP S5773942A
Authority
JP
Japan
Prior art keywords
film
taper
pattern
plasma
nitride film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55150354A
Other languages
Japanese (ja)
Inventor
Masaharu Yorikane
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55150354A priority Critical patent/JPS5773942A/en
Publication of JPS5773942A publication Critical patent/JPS5773942A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To prevent the disconnection of wires of the upper layer without forming a sharp step at the etched pattern by selectively etching a conductive layer or an insulation layer using a mask having a taper at the end of the pattern. CONSTITUTION:Contact holes are made at an oxide film 22 on a substrate 21 forming an element, and this is covered with an Al film 24 and a nitride film 25 of plasma CVD. After the surface of the nitride film 25 is made rough by implanting Ar, ions, the film 25 is plasma-etched by a resist mask to form a taper 26 at the end of the pattern. Then removing the film 25 by plasma of CCl4 group, Al pattern is formed with a taper 27 at the edge. Next a plasma nitride film is formed as a film 28 between layers for example, and Al wiring 30 is arranged at the upper layer. Thus steps at the multilayer wiring structure can be made easy, by processing a mask material of etching rate suitable as a etching material to form a taper.
JP55150354A 1980-10-27 1980-10-27 Manufacture of semiconductor device Pending JPS5773942A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55150354A JPS5773942A (en) 1980-10-27 1980-10-27 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55150354A JPS5773942A (en) 1980-10-27 1980-10-27 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5773942A true JPS5773942A (en) 1982-05-08

Family

ID=15495150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55150354A Pending JPS5773942A (en) 1980-10-27 1980-10-27 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5773942A (en)

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