JPS5775024A - Schmitt trigger circuit - Google Patents

Schmitt trigger circuit

Info

Publication number
JPS5775024A
JPS5775024A JP55151924A JP15192480A JPS5775024A JP S5775024 A JPS5775024 A JP S5775024A JP 55151924 A JP55151924 A JP 55151924A JP 15192480 A JP15192480 A JP 15192480A JP S5775024 A JPS5775024 A JP S5775024A
Authority
JP
Japan
Prior art keywords
flop
flip
threshold voltages
circuit
trigger circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55151924A
Other languages
Japanese (ja)
Inventor
Eiji Masuda
Hiroshi Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55151924A priority Critical patent/JPS5775024A/en
Publication of JPS5775024A publication Critical patent/JPS5775024A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0377—Bistables with hysteresis, e.g. Schmitt trigger

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To obtain a Schmitt circuit of a wide hysteresis width, by setting properly threshold voltages of inverter circuits connected to set input and reset input systems of a flip-flop. CONSTITUTION:An RS flip-flop 18 consists of an OR/NAND circuit 16 consisting of CMOS transistors and an inverter circuit 15. The set input system of the RS flip- flop 18 is provided with CMOS inverters 11 and 12, and the reset input system is provided with CMOS inverters 13 and 14, thus constituting a Schmitt circuit Respective threshold voltages VT1, VT2, VT3 and VT4 of inverters 11, 12, 13, and 14 are set to satisfy VT1=VT4>VT2 VT3, and a hysteresis determined by these threshold voltages is obtained.
JP55151924A 1980-10-29 1980-10-29 Schmitt trigger circuit Pending JPS5775024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55151924A JPS5775024A (en) 1980-10-29 1980-10-29 Schmitt trigger circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55151924A JPS5775024A (en) 1980-10-29 1980-10-29 Schmitt trigger circuit

Publications (1)

Publication Number Publication Date
JPS5775024A true JPS5775024A (en) 1982-05-11

Family

ID=15529168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55151924A Pending JPS5775024A (en) 1980-10-29 1980-10-29 Schmitt trigger circuit

Country Status (1)

Country Link
JP (1) JPS5775024A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571504A (en) * 1982-10-21 1986-02-18 Tokyo Shibaura Denki Kabushiki Kaisha Schmitt trigger circuit with selection circuit
JPH0290066A (en) * 1988-09-27 1990-03-29 Nec Corp Hysteresis circuit
US6340907B2 (en) 2000-02-08 2002-01-22 Nec Corporation Schmitt trigger circuit having independent threshold voltage setting to provide hysteresis
US20220286117A1 (en) * 2021-03-05 2022-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Input buffer circuit
US12633920B2 (en) 2024-02-26 2026-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Input buffer circuit having variable threshold circuits

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5453948A (en) * 1977-10-07 1979-04-27 Hitachi Ltd Oscillation circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5453948A (en) * 1977-10-07 1979-04-27 Hitachi Ltd Oscillation circuit

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571504A (en) * 1982-10-21 1986-02-18 Tokyo Shibaura Denki Kabushiki Kaisha Schmitt trigger circuit with selection circuit
JPH0290066A (en) * 1988-09-27 1990-03-29 Nec Corp Hysteresis circuit
US6340907B2 (en) 2000-02-08 2002-01-22 Nec Corporation Schmitt trigger circuit having independent threshold voltage setting to provide hysteresis
US20220286117A1 (en) * 2021-03-05 2022-09-08 Taiwan Semiconductor Manufacturing Company, Ltd. Input buffer circuit
US11863189B2 (en) * 2021-03-05 2024-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Input buffer circuit
US12652029B2 (en) 2021-03-05 2026-06-09 Taiwan Semiconductor Manufacturing Company, Ltd. Input buffer circuit
US12633920B2 (en) 2024-02-26 2026-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Input buffer circuit having variable threshold circuits

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