JPS5776650A - Loop counter control system - Google Patents
Loop counter control systemInfo
- Publication number
- JPS5776650A JPS5776650A JP15317880A JP15317880A JPS5776650A JP S5776650 A JPS5776650 A JP S5776650A JP 15317880 A JP15317880 A JP 15317880A JP 15317880 A JP15317880 A JP 15317880A JP S5776650 A JPS5776650 A JP S5776650A
- Authority
- JP
- Japan
- Prior art keywords
- lpc
- loop
- contents
- looping
- loop counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/15—Correlation function computation including computation of convolution operations
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Complex Calculations (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE:To vary the number of times of internal looping according to the number of times of external looping of double loop regarding autocorrelation arithmetic, by adding the readout output of a read-only memory and the contents of a loop counter by an adding circuit and by setting the sum in the loop counter. CONSTITUTION:For arithmetic shown by expression (1), a frequency i=c+n-d of internal looping should be varied with a frequency n=a-b of external looping. With an instruction LS (loop start), the readout output a-b+M of a ROM is set in a loop counter LPC and also set as a frequency of looping in a stack ST. With every instruction LE (loop end), the LPC is increased in contents to return to the starting LS or LSM (loop start modify) of a loop and when the contents of the LPC have a maximum value M, the contents of the ST are set in the LPC. When the control returns to the LSM, the readout output c-d+b of the ROM and the contents of the LPC are added by an adding circuit ADD, whose sum output is set in the LPC through a selector SEL2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15317880A JPS5776650A (en) | 1980-10-31 | 1980-10-31 | Loop counter control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15317880A JPS5776650A (en) | 1980-10-31 | 1980-10-31 | Loop counter control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5776650A true JPS5776650A (en) | 1982-05-13 |
| JPS6133228B2 JPS6133228B2 (en) | 1986-08-01 |
Family
ID=15556749
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15317880A Granted JPS5776650A (en) | 1980-10-31 | 1980-10-31 | Loop counter control system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5776650A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011065145A1 (en) * | 2009-11-24 | 2011-06-03 | 日本電気株式会社 | Processor, and method of loop iteration control by processor |
-
1980
- 1980-10-31 JP JP15317880A patent/JPS5776650A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011065145A1 (en) * | 2009-11-24 | 2011-06-03 | 日本電気株式会社 | Processor, and method of loop iteration control by processor |
| JP5692089B2 (en) * | 2009-11-24 | 2015-04-01 | 日本電気株式会社 | Processor and loop number control method by processor |
| US9286066B2 (en) | 2009-11-24 | 2016-03-15 | Nec Corporation | Processor, and method of loop count control by processor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6133228B2 (en) | 1986-08-01 |
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